Semiconductor device and method of manufacturing the same

ABSTRACT

An upper surface of a plug (PL 1 ) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate ( 1 S), completing a CMP method for forming the plug (PL 1 ) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL 1 ) and a wiring (W 1 ) in a vertical direction can be ensured. Also, the wiring (W 1 ) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.

This is a Continuation of U.S. application Ser. No. 16/033,962 filedJul. 12, 2018, which is a Continuation of U.S. application Ser. No.15/092,151 (patented as U.S. Pat. No. 10,049,984), filed Apr. 6, 2016,which is a Continuation of U.S. application Ser. No. 14/683,788(patented as U.S. Pat. No. 9,337,016) filed on Apr. 10, 2015, which is adivisional application based upon U.S. patent application Ser. No.13/704,113 (patented as U.S. Pat. No. 9,030,014) filed Dec. 13, 2012,which is a National Stage Entry of International Application No.PCT/JP2010/060050 filed Jun. 14, 2010, the contents of all of which areincorporated herein by reference in their entirety.

TECHNICAL FIELD

The present invention relates to a semiconductor device and a method ofmanufacturing the same, and, more particularly, the present inventionrelates to a semiconductor device having the lowermost-layer wiringformed as a buried wiring and relates to a method of manufacturing thesame.

BACKGROUND ART

Along with demands for microfabrication, high integration, and highspeed of a semiconductor device, it is required to reduce a wiringresistance, reduce an inter-wiring capacitance, and improve reliabilityof a wiring. For the reduction of the wiring resistance, a copper (Cu)wiring having a lower resistance than that of a conventional aluminum(Al) alloy is used.

For the reduction of the inter-wiring capacitance, instead ofconventional silicon oxide (SiO₂), an insulating film having a lowerdielectric constant than that of the silicon oxide (hereinafter, whichis referred to as a low dielectric constant film) is used as aninterlayer insulating film of the wiring.

Japanese Patent Application Laid-Open Publication No. 2004-158832(Patent Document 1) discloses a technique related to a multilayeredwiring using a SiOC film as the low dielectric constant film for theinterlayer insulating film.

Meanwhile, in a viewpoint of ensuring reliability of connection betweena plug and a wiring, the following techniques are disclosed.

Japanese Patent Application Laid-Open Publication No. 2006-339623(Patent Document 2) discloses a technique for preventing occurrence ofvoids upon forming a metal layer 104 by selectively etching aninterlayer insulating film 102 so that a surface of the uppermostportion of a contact plug 103 in the lowermost layer is lower than asurface of the uppermost portion of the interlayer insulating film 102,and then, forming the metal layer 104 on the interlayer insulating film102.

Also, Japanese Patent Application Laid-Open Publication No. 2006-73635(Patent Document 3) discloses a technique for forming a small upperportion of a contact 7 by processing a conductive material deposited onan interlayer insulating film 6.

PRIOR ART DOCUMENTS Patent Documents

Patent Document 1: Japanese Patent Application Laid-Open Publication No.2004-158832

Patent Document 2: Japanese Patent Application Laid-Open Publication2006-339623

Patent Document 3: Japanese Patent Application Laid-Open Publication2006-73635

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention

In recent years, further microfabrication of a semiconductor device hasbeen advanced, and it has been desired to improve performance thereofwithout various failures.

A preferred aim of the present invention is to improve electricperformance of a semiconductor device, and, more particularly, is toreduce delay of a signal transmitted via a wiring.

Also, another preferred aim of the present invention is to improvereliability of a semiconductor device, and, more particularly, is toimprove reliability of a wiring.

Further, still another preferred aim of the present invention is toimprove electric performance of a semiconductor device and improvereliability of the semiconductor device, and, more particularly, is toreduce delay of a signal transmitted via a wiring and improvereliability of the wiring.

The above and other preferred aims and novel characteristics of thepresent invention will be apparent from the description of the presentspecification and the accompanying drawings.

Means for Solving the Problems

The typical ones of the inventions disclosed in the present applicationwill be briefly described as follows.

A method of manufacturing a semiconductor device according to a typicalembodiment includes: (a) a step of forming a first interlayer insulatingfilm on a semiconductor substrate; (b) a step of forming a first contacthole in the first interlayer insulating film; and (c) after the step of(b), a step of forming a first conductive film on the semiconductorsubstrate so as to bury the first conductive film inside the firstcontact hole. Further, the method includes: (d) a step of removing thefirst conductive film outside the first contact hole so as to form afirst plug made of the first conductive film; (e) after the step of (d),a step of making an upper surface of the first interlayer insulatingfilm to recede so that the upper surface of the first interlayerinsulating film is lower than an upper surface of the first plug; and(f) after the step of (e), a step of forming a second interlayerinsulating film having a lower dielectric constant than that of siliconoxide, on the semiconductor substrate. Still further, the methodincludes: (g) a step of forming a first wiring trench in the secondinterlayer insulating film so that a part of the first plug is exposedand so that a lower surface thereof is lower than an upper surface ofthe first plug; (h) after the step of (g), a step of forming a secondconductive film on the semiconductor substrate so as to bury the secondconductive film inside the first wiring trench; and (i) a step ofremoving the second conductive film outside the first wiring trench soas to form a first wiring made of the second conductive film andconnected to the first plug.

Also, a semiconductor device according to a typical embodiment includes:a first interlayer insulating film formed on a semiconductor substrate;a first plug formed inside the first interlayer insulating film; asecond interlayer insulating film formed on the first insulating filmand having a lower dielectric constant than that of silicon oxide; and afirst buried wiring formed inside the second interlayer insulating filmand connected to the first plug. And, an upper surface of the first plugis formed at a position higher than an upper surface of the firstinterlayer insulating film, and a lower surface of the first buriedwiring is formed at a position lower than the upper surface of the firstplug.

Effects of the Invention

The effects obtained by typical aspects of the present inventiondisclosed in the present application will be briefly described below.

In a semiconductor device of the present invention, electric performanceof the semiconductor device can be improved. More particularly, delay ofa signal transmitted via a wiring can be reduced.

Also, effects obtainable by other means will be briefly described below.

In a semiconductor device of the present invention, reliability thereofcan be improved. More particularly, reliability of a wiring can beimproved.

Further, in a semiconductor device of the present invention, electricperformance of the semiconductor device can be improved, and besides,reliability of the semiconductor device can be improved. Moreparticularly, delay of a signal transmitted via a wiring can be reduced,and besides, reliability of a wiring can be improved.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is a plan view of a principal part of a semiconductor deviceaccording to a first embodiment of the present invention;

FIG. 2 is a plan view of a principal part of the semiconductor deviceaccording to the first embodiment of the present invention;

FIG. 3 is a cross-sectional view of a principal part (cross-sectionalview taken along a line A-A) of the semiconductor device according tothe first embodiment of the present invention;

FIG. 4 is a cross-sectional view of a principal part (cross-sectionalview taken along the line A-A) of the semiconductor device according tothe first embodiment of the present invention in a manufacturing stepthereof;

FIG. 5 is a cross-sectional view of the principal part (cross-sectionalview taken along the line A-A) of the semiconductor device in amanufacturing step thereof continued from FIG. 4;

FIG. 6 is a cross-sectional view of the principal part (cross-sectionalview taken along the line A-A) of the semiconductor device in amanufacturing step thereof continued from FIG. 5;

FIG. 7 is a cross-sectional view of the principal part (cross-sectionalview taken along the line A-A) of the semiconductor device in amanufacturing step thereof continued from FIG. 6;

FIG. 8 is a cross-sectional view of the principal part (cross-sectionalview taken along the line A-A) of the semiconductor device in amanufacturing step thereof continued from FIG. 7;

FIG. 9 is a cross-sectional view of the principal part (cross-sectionalview taken along the line A-A) of the semiconductor device in amanufacturing step thereof continued from FIG. 8;

FIG. 10 is a cross-sectional view of the principal part (cross-sectionalview taken along the line A-A) of the semiconductor device in amanufacturing step thereof continued from FIG. 9;

FIG. 11 is a cross-sectional view in a vicinity of an edge portion of awafer;

FIG. 12 is an explanatory diagram of a step of forming a contact hole;

FIG. 13 is an explanatory diagram of a step of forming a contact hole;

FIG. 14 is an explanatory diagram of another step of forming the contacthole;

FIG. 15 is an explanatory diagram of still another step of forming thecontact hole;

FIG. 16 is an explanatory diagram of still another step of forming thecontact hole;

FIG. 17 is a cross-sectional view in the vicinity of the edge portion ofthe wafer;

FIG. 18 is a cross-sectional view in the vicinity of the edge portion ofthe wafer;

FIG. 19 is a cross-sectional view of the principal part (cross-sectionalview taken along the line A-A) of the semiconductor device in amanufacturing step thereof continued from FIG. 10;

FIG. 20 is a cross-sectional view of the principal part (cross-sectionalview taken along the line A-A) of the semiconductor device in amanufacturing step thereof continued from FIG. 19;

FIGS. 21A and 21B are cross-sectional views of the principal part(cross-sectional view taken along the line A-A) of the semiconductordevice in a manufacturing step thereof continued from FIG. 20;

FIG. 22 is an enlarged cross-sectional view of a principal part of anenlarged periphery of a region where a plug and a wiring are connectedin FIG. 21A;

FIG. 23 is a cross-sectional view of the principal part (cross-sectionalview taken along the line A-A) of the semiconductor device in amanufacturing step thereof continued from FIG. 21;

FIG. 24 is a plan view of the principal part of the same portion as thatillustrated in FIG. 2 in a case that lithography misalignment does notoccur;

FIG. 25 is a cross-sectional view of a principal part taken along a lineA2-A2 in FIG. 24;

FIG. 26 is a cross-sectional view of a principal part taken along a lineB2-B2 in FIG. 24;

FIG. 27 is a cross-sectional view of a principal part (cross-sectionalview taken along a line A-A) of a semiconductor device according to asecond embodiment of the present invention;

FIG. 28 is a cross-sectional view of the principal part (cross-sectionalview taken along the line A-A) of the semiconductor device according tothe second embodiment of the present invention in a manufacturing stepthereof;

FIG. 29 is a cross-sectional view of the principal part (cross-sectionalview taken along the line A-A) of the semiconductor device in amanufacturing step thereof continued from FIG. 28;

FIGS. 30A and 30B are cross-sectional views of the principal parts(cross-sectional views taken along the line A-A) of the semiconductordevice in a manufacturing step thereof continued from FIG. 29;

FIG. 31 is a cross-sectional view of the principal part (cross-sectionalview taken along the line A-A) of the semiconductor device in amanufacturing step thereof continued from FIGS. 30A and 30B;

FIG. 32 is an enlarged cross-sectional view of a principal part of anenlarged periphery of a region where a plug and a wiring are connectedin FIG. 27;

FIG. 33 is an enlarged cross-sectional view of a principal part of anenlarged periphery of a region where a plug and a wiring are connectedin FIG. 31;

FIG. 34 is a cross-sectional view of a principal part (cross-sectionalview taken along a line A-A) of a semiconductor device according to athird embodiment of the present invention;

FIG. 35 is a cross-sectional view of the principal part (cross-sectionalview taken along the line A-A) of the semiconductor device according tothe third embodiment of the present invention in a manufacturing stepthereof;

FIG. 36 is a cross-sectional view of the principal part (cross-sectionalview taken along the line A-A) of the semiconductor device in amanufacturing step thereof continued from FIG. 35;

FIG. 37 is a cross-sectional view of the principal part (cross-sectionalview taken along the line A-A) of the semiconductor device in amanufacturing step thereof continued from FIG. 36;

FIG. 38 is an enlarged cross-sectional view of a principal part of anenlarged periphery of a region where a plug and a wiring are connectedin FIG. 34;

FIG. 39 is a cross-sectional view of a principal part (cross-sectionalview taken along a line A-A) of a semiconductor device according to afourth embodiment of the present invention;

FIG. 40 is a cross-sectional view of the principal part (cross-sectionalview taken along the line A-A) of the semiconductor device according tothe fourth embodiment of the present invention in a manufacturing stepthereof;

FIG. 41 is a cross-sectional view of the principal part (cross-sectionalview taken along the line A-A) of the semiconductor device in amanufacturing step thereof continued from FIG. 40;

FIG. 42 is a cross-sectional view of the principal part (cross-sectionalview taken along the line A-A) of the semiconductor device in amanufacturing step thereof continued from FIG. 41;

FIG. 43 is an enlarged cross-sectional view of a principal part of anenlarged periphery of a region where a plug and a wiring are connectedin FIG. 39;

FIG. 44 is a cross-sectional view of a principal part (cross-sectionalview taken along a line A-A) of a semiconductor device according to afifth embodiment of the present invention;

FIG. 45 is a cross-sectional view of the principal part (cross-sectionalview taken along the line A-A) of the semiconductor device according tothe fifth embodiment of the present invention in a manufacturing stepthereof;

FIG. 46 is a cross-sectional view of the principal part (cross-sectionalview taken along the line A-A) of the semiconductor device in amanufacturing step thereof continued from FIG. 45;

FIG. 47 is a cross-sectional view of the principal part (cross-sectionalview taken along the line A-A) of the semiconductor device in amanufacturing step thereof continued from FIG. 46;

FIG. 48 is a cross-sectional view of the principal part (cross-sectionalview taken along the line A-A) of the semiconductor device in amanufacturing step thereof continued from FIG. 47;

FIG. 49 is a cross-sectional view of the principal part (cross-sectionalview taken along the line A-A) of the semiconductor device in amanufacturing step thereof continued from FIG. 48;

FIG. 50 is cross-sectional views of principal parts (cross-sectionalviews taken along a line A-A and a line C-C) of a semiconductor deviceaccording to a sixth embodiment of the present invention;

FIG. 51 is cross-sectional views of the principal parts (cross-sectionalviews taken along the line A-A and the line C-C) of the semiconductordevice according to the sixth embodiment of the present invention in amanufacturing step thereof;

FIG. 52 is cross-sectional views of the principal parts (cross-sectionalviews taken along the line A-A and the line C-C) of the semiconductordevice in a manufacturing step thereof continued from FIG. 51;

FIG. 53 is enlarged cross-sectional views of principal parts of anenlarged periphery of a region where a plug and a wiring are connectedin FIG. 50;

FIG. 54 is cross-sectional views of principal parts (cross-sectionalviews taken along a line A-A and a line C-C) of a semiconductor deviceaccording to the sixth embodiment of the present invention as a firstmodification example;

FIG. 55 is cross-sectional views of principal parts (cross-sectionalviews taken along a line A-A and a line C-C) of a semiconductor deviceaccording to the sixth embodiment of the present invention as a secondmodification example;

FIG. 56 is cross-sectional views of principal parts (cross-sectionalviews taken along a line A-A and a line C-C) of a semiconductor deviceaccording to the sixth embodiment of the present invention as a thirdmodification example;

FIG. 57 is cross-sectional views of principal parts (cross-sectionalviews taken along a line A-A and a line C-C) of a semiconductor deviceaccording to the sixth embodiment of the present invention as a fourthmodification example;

FIG. 58 is cross-sectional views of principal parts (cross-sectionalviews taken along a line A-A and a line C-C) of a semiconductor deviceaccording to the sixth embodiment of the present invention as a fifthmodification example;

FIG. 59 is cross-sectional views of principal parts (cross-sectionalviews taken along a line A-A and a line C-C) of a semiconductor deviceaccording to a seventh embodiment of the present invention;

FIG. 60 is a cross-sectional view of a principal part of a semiconductordevice as a comparative example studied by the present inventor, in amanufacturing step thereof;

FIG. 61 is a cross-sectional view of the principal part of thesemiconductor device as the comparative example in a manufacturing stepthereof continued from FIG. 60;

FIG. 62 is a cross-sectional view of the principal part of thesemiconductor device as the comparative example in a manufacturing stepthereof continued from FIG. 61;

FIG. 63 is a cross-sectional view of the principal part of thesemiconductor device as the comparative example in a manufacturing stepthereof continued from FIG. 62;

FIG. 64 is a cross-sectional view of the principal part of thesemiconductor device as the comparative example in a manufacturing stepthereof continued from FIG. 63; and

FIG. 65 is a cross-sectional view of the principal part of thesemiconductor device as the comparative example in a manufacturing stepthereof continued from FIG. 64.

DESCRIPTIONS OF THE PREFERRED EMBODIMENTS

In the embodiments described below, the invention will be described in aplurality of sections or embodiments when required as a matter ofconvenience. However, these sections or embodiments are not irrelevantto each other unless otherwise stated, and the one relates to the wholeor a part of the other as a modification example, details, or asupplementary explanation thereof. Also, in the embodiments describedbelow, when referring to the number of elements (including number ofpieces, values, amount, range, and the like), the number of the elementsis not limited to a specific number unless otherwise stated or exceptthe case where the number is apparently limited to a specific number inprinciple. The number larger or smaller than the specified number isalso applicable. Further, in the embodiments described below, it goeswithout saying that the components (including element steps) are notalways indispensable unless otherwise stated or except the case wherethe components are apparently indispensable in principle. Similarly, inthe embodiments described below, when the shape of the components,positional relation thereof, and the like are mentioned, thesubstantially approximate and similar shapes and the like are includedtherein unless otherwise stated or except the case where it isconceivable that they are apparently excluded in principle. The samegoes for the numerical value and the range described above.

Also, the same components are denoted by the same reference symbolsthroughout the drawings for describing the embodiments in principle, andthe repetitive description thereof is omitted. Note that hatching isused even in a plan view so as to make the drawings easy to see in somecases. Further, hatching is omitted even in a cross-sectional view so asto make the drawings easy to see in some cases.

Each of FIGS. 60 to 65 is a cross-sectional view of a principal partillustrating a step of manufacturing a semiconductor device studied bythe present inventor as a comparative example. Hereinafter, withreference to FIGS. 60 to 65, the steps (steps P1 to P6) of manufacturingthe semiconductor device studied by the present inventor as thecomparative example will be described.

(Step P1)

First, as illustrated in FIG. 60, a MISFET Q₁₀₁ is formed on a mainsurface of a semiconductor substrate 101S by using a publicly-knownmethod. More specifically, an element isolation region STI101, a p-typewell PWL101, a gate insulating film GI101, a gate electrode G101, ashallow low-concentration n-type impurity diffusion region EX101, asidewall SW101, a deep impurity diffusion region NR101, and a metalsilicide layer NSF101 are sequentially formed. Then, an interlayerinsulating film PIL101 is formed on the semiconductor substrate 101S soas to cover the MISFET Q₁₀₁. As illustrated in FIG. 60, the interlayerinsulating film PIL101 is formed of a stacked film made of a siliconnitride film SN101, an O₃-TEOS film OTS101, and a plasma TEOS filmPTS101 as an insulating film.

(Step 2)

Next, as illustrated in FIG. 61, a contact hole CNT101 is formed in theinterlayer insulating film PIL101, and then, a conductive film CF101 isformed on the interlaying insulation PIL101 so that the conductive filmCF101 is buried inside the contact hole ONT101.

(Step 3)

Next, as illustrated in FIG. 62, an unnecessary portion of theconductive film CF101 formed outside the contact hole CNT101 is removedso that the interlayer insulating film PIL101 is exposed. By this step,a plug PL101 is formed. In this step, the plug PL101 is formed so thatan upper surface of the plug PL101 is almost as high as an upper surfaceof the interlayer insulating film PIL101 or so that the height of theupper surface of the plug PIL101 is lower than the height of the uppersurface of the interlayer insulating film PIL101. FIG. 62 illustratesthe case that the upper surface of the plug PL101 is formed almost ashigh as the upper surface of the interlayer insulating film PIL101.

(Step 4)

Next, as illustrated in FIG. 63, an interlayer insulating film WIL101 isformed on the plug PL101 and the interlayer insulating film PIL101. Theinterlayer insulating film WIL101 is formed of a low dielectric constantfilm on purpose to reduce an inter-wiring capacitance of a wiring to beformed in a later step. A thickness of the interlayer insulating filmWIL101 is, for example, 60 nm.

(Step 5)

Next, as illustrated in FIG. 64, by processing the interlayer insulatingfilm WIL101 and the interlayer insulating film PIL101, a wiring trenchWT101 for a buried wiring is formed inside the interlayer insulatingfilm WIL101 and the interlayer insulating film PIL101. In theabove-described step P3, the upper surface of the plug PL101 is formedalmost as high as the upper surface of the interlayer insulating filmPIL101 or formed lower than the upper surface of the interlayerinsulating film PIL101. Therefore, in order to ensure a connectionbetween a wiring (W101) to be formed in a later step and the plug PL101,the wiring trench WT101 is formed inside the interlayer insulating filmPIL101 in a state of, for example, 30 nm embedded (buried) from theupper surface of the interlayer insulating film PIL101. That is, thelowermost surface of the wiring trench WT101 is formed at a positionwhich is 30 nm lower than the upper surface of the plug PL101. A depthof the wiring trench WT101 is, for example, 90 nm. In FIG. 64, thisembedding depth is illustrated as a length L101.

(Step 6)

Next, as illustrated in FIG. 65, a wiring W101 is formed by burying aconductive film CF102 into the wiring trench WT101. At this time, by theformation of the wiring trench WT101 inside the interlayer insulatingfilm PIL101 so as to be embedded (buried) therein by the length L101from the upper surface of the interlayer insulating film PIL101, thewiring W101 formed by burying the conductive film CF102 inside thewiring trench WT101 is also formed inside the interlayer insulating filmPIL101 so as to be embedded (buried) therein by the length L101 from theupper surface of the interlayer insulating film PIL101. As a result, aconnection between the wiring W101 and the plug PL101 is ensured by thelength L101 in a direction perpendicular to the semiconductor substrate101S. That is, in the manufacturing steps as the comparative exampledescribed with reference to FIGS. 60 to 65, the connection between theplug PL101 and the wiring W101 in a vertical direction is ensured byembedding (burying) the wiring trench WT101 (and the wiring W101 buriedtherein) inside the interlayer insulating film PIL101 by a length (=thelength L101) required for ensuring the connection.

However, the present inventor has newly found out that the followingproblems arise in the manufacturing steps as described above (themanufacturing steps of the comparative example described with referenceto FIGS. 60 to 65).

In spite of the fact that the interlayer insulating film WIL101 isformed of the low dielectric constant film, the wiring W101 is embedded(buried) inside the interlayer insulating film PIL101 which is notformed of a low dielectric constant film, by the length L101, andtherefore, it is difficult to reduce the inter-wiring capacitance. Also,since the wiring W101 is embedded (buried) inside the interlayerinsulating film PIL101 by the length L101, a distance between the wiringW101 and the MISFET Q₁₀₁ is shortened, and therefore, reliabilitybetween the wiring W101 and the gate electrode G101 of the MISFET Q₁₀₁is reduced. Further, since the wiring W101 is embedded (buried) insidethe interlayer insulating film PIL101 by the length L101, a distancebetween the wiring W101 and the O₃-TEOS film OTS101 is shortened.However, insulation properties of the O₃-TEOS film OTS101 are notexcellent, and therefore, reliability of the wiring W101 is reduced byshortening the distance between the wiring W101 and the O₃-TEOS filmOTS101. Still further, although not illustrated, the wiring trench tendsto be formed by deeper embedding (that is, the wiring trench tends to bedeeper) in a case that a wiring having a large wiring width is formedthan a case that a wiring having a small wiring width is formed upon theformation of the wiring trench. Therefore, each of the above-describedproblems becomes more obvious.

Hereinafter, the invention made by the present inventor in considerationof the above-described problems will be specifically explained based onembodiments.

First Embodiment

A first embodiment is applied to, for example, a semiconductor device inwhich an n-channel-type MISFET (MISFET: Metal Insulator SemiconductorField Effect Transistor) and a p-channel-type MISFET are formed on asemiconductor substrate (semiconductor wafer) 1S, and to a method ofmanufacturing the same. The semiconductor device and the method ofmanufacturing the same of the first embodiment will be explained withreference to the drawings.

Each of FIGS. 1 and 2 is a plan view of the semiconductor deviceaccording to the first embodiment. FIGS. 1 and 2 illustrate the sameplanar region as each other in the semiconductor device of the firstembodiment, and FIG. 2 corresponds to a drawing obtained by overlaying afirst-layer wiring including wirings W1 and W1 a on FIG. 1. While FIGS.1 and 2 are plan views, hatching is attached to the first-layer wiringincluding the wirings W1 and W1 a in FIG. 2, and hatching is attached toa gate electrode G1, an n-type semiconductor region NS1, and p-typesemiconductor regions PS1 and PS2 in FIG. 1, in order to easily see thedrawings.

Each of FIGS. 1 and 2 illustrates a region where an n-channel-typeMISFET Q₁ and a p-channel-type MISFET Q₂ are formed on a main surface ofthe semiconductor substrate 1S. More specifically, in the planar regionillustrated in FIGS. 1 and 2, the gate electrode G1, the n-typesemiconductor region NS1 which is a source region or a drain region ofthe n-channel-type MISFET Q₁, and the p-type semiconductor region PS1which is a source region or a drain region of the p-channel-type MISFETQ₂ are formed. Further, a plug PL1 connected to the p-type semiconductorregion PS1 or the n-type semiconductor region NS1, a plug PL2 connectedto the p-type semiconductor region PS2, the wiring W1 which is thefirst-layer wiring connected to the plug PL1, the wiring W2 which is thefirst-layer wiring connected to the plug PL2, and others are formedtherein.

Hereinafter, a cross section taken along a line A-A illustrated in FIGS.1 and 2 is referred to as a cross section A, a cross section taken alonga line B-B illustrated in FIGS. 1 and 2 is referred to as a crosssection B, and a cross section taken along a line C-C illustrated inFIGS. 1 and 2 is referred to as a cross section C. Hereinafter, for thepurpose of simplification, the semiconductor device and the method ofmanufacturing the same according to the first embodiment will beexplained with reference to the cross section A where the n-channel-typeMISFET Q₁ is formed.

FIG. 3 is a cross-sectional view of a principal part of thesemiconductor device of the first embodiment, and illustrates the crosssection A taken along the line A-A in FIGS. 1 and 2. Hereinafter, astructure of the semiconductor device according to the first embodimentwill be specifically explained.

As illustrated in FIG. 3, an element isolation region STI is formed inthe semiconductor substrate 1S, and a p-type well PWL1 is formed in anactive region of the semiconductor substrate 1S which is partitioned(defined) by this element isolation region STI. The p-type well PWL1 isformed of a p-type semiconductor region formed by introducing a p-typeimpurity such as boron (B) into the semiconductor substrate 1S.

A gate insulating film GI1 is formed on the p-type well PWL1 (thesemiconductor substrate 1S), and the gate electrode G1 is formed on thisgate insulating film GI1. The gate insulating film GI1 is formed of, forexample, a silicon oxide film as an insulating film. The gate electrodeG1 is formed of, for example, a polycrystalline silicon film and a metalsilicide layer (a metal silicide film) NSF1 formed on an upper portionof this polycrystalline silicon film as a conductive film. The metalsilicide layer NSF1 configuring a part of the gate electrode G1 isformed in order to decrease a resistance of the gate electrode G1.

On both side walls of the gate electrode G1, a sidewall (sidewallspacer, sidewall insulating film) SW1 made of an insulating film isformed. A shallow impurity diffusion region (an extension region) EX1which is a semiconductor region is formed in the p-type well PWL1 (thesemiconductor substrate 1S) right below this sidewall SW1. This shallowimpurity diffusion region EX1 is an n-type semiconductor region, and isformed so as to be aligned with the gate electrode G1. And, a deepimpurity diffusion region NR1 which is a semiconductor region is formedoutside this shallow impurity diffusion region EX1. This deep impuritydiffusion region NR1 is also an n-type semiconductor region, and isformed so as to be aligned with the sidewall SW1. On a surface (an upperportion) of the deep impurity diffusion region NR1, the metal silicidelayer NSF1 is formed in order to decrease the resistance. The deepimpurity diffusion region NR1 has a higher impurity concentration(n-type impurity concentration) and a deeper junction depth than thoseof the shallow impurity diffusion region EX1. By the shallow impuritydiffusion region EX1 and the deep impurity diffusion region NR1, then-type semiconductor region NS1 serving as the source region or thedrain region is formed.

In this manner, the n-channel-type MISFET Q₁ is formed in the crosssection A. Also, although not illustrated here, a cross-sectionalstructure of the p-channel-type MISFET Q₂ almost supports a structure inwhich the p-type well PWL1 is to be an n-type well, each of the shallowimpurity diffusion region EX1 and the deep impurity diffusion region NR1is to be a p-type semiconductor region, and the n-type semiconductorregion NS1 is to be a p-type semiconductor region PS1 in FIG. 3 wherethe re-channel-type MISFET Q₁ is formed. The polycrystalline siliconfilm in a portion forming the gate electrode G1 of the n-channel-typeMISFET Q₁ is preferably an n-type polycrystalline silicon film (dopedpolysilicon film), and the polycrystalline silicon film in a portionforming the gate electrode G1 of the p-channel-type MISFET Q₂ ispreferably a p-type polycrystalline silicon film (doped polysiliconfilm).

By the n-channel-type MISFET Q₁ and the p-channel-type MISFET Q₂ formedon the main surface of the semiconductor substrate 1S, for example, aword driver, a sense amplifier, a control circuit, or others isconfigured, and besides, a CPU (circuit), a RAM (circuit), an analogcircuit, an I/O circuit, or others is configured.

Subsequently, a wiring structure connected to the re-channel-type MISFETQ₁ will be explained.

As illustrated in FIG. 3, on the main surface of the semiconductorsubstrate 1S (that is, on the n-channel-type MISFET Q₁), the interlayerinsulating film PIL is formed so as to cover the n-channel-type MISFETQ₁. The interlayer insulating film PIL is formed of, for example, astacked film formed of: an insulating film SN made of a silicon nitridefilm as an insulating film; and an insulating film SO made of a siliconoxide film as an insulating film. In the insulating film SN and theinsulating film SO forming the interlayer insulating film PIL, theinsulating film SN is on a lower-layer side and the insulating film SOis on an upper-layer side, and therefore, the insulating film SO isformed above the insulating film SN.

In this interlayer insulating film PIL, a contact hole (through hole,hole) CNT1 is formed so as to penetrate through the interlayerinsulating film PIL and reach the metal silicide layer NSF1 (that is,the metal silicide layer NSF1 above the deep impurity diffusion regionNR1) forming the n-type semiconductor region NS1. Therefore, from abottom portion of the contact hole CNT1, the metal silicide layer NSF1formed above the deep impurity diffusion region NR1 is exposed.

Inside (in side walls and a bottom portion of) the contact hole CNT1, abarrier conductor film PBM is formed of, for example, a stacked filmformed of a titanium film (a Ti film) and a titanium nitride film (a TiNfilm) as a conductive film, and a conductor film TF is formed of, forexample, a tungsten film as a conductive film so as to be buried in thecontact hole GNT1. In this manner, by burying the barrier conductor filmPBM and the conductor film TF into the contact hole CNT1, the conductiveplug PL1 is formed. Since the plug PL1 is formed so as to fill thecontact hole CNT1 of the interlayer insulating film PIL, the plug PL1can be regarded as being formed inside the interlayer insulating filmPIL.

While the plug PL1 is a connecting conductor portion and is buriedinside the contact hole CNT1, a height of an upper surface of theinterlayer insulating film PIL is lower than a height of an uppersurface of the plug PL1. That is, the height of the upper surface of theplug PL1 is higher than the upper surface of the interlayer insulatingfilm PIL. In other words, a part of the plug PL1 protrudes (projectsout) from the upper surface of the interlayer insulating film PIL. Whilethe plug PL1 is formed of the barrier conductor film PBM and theconductor film TF as described above, side surfaces and a bottom surfaceof the plug PL1 are formed of the barrier conductor film PBM, and theother parts (mainly an inside) thereof are formed of the conductor filmTF.

Note that, in the present application, it is set that a height or aheight position of each of an upper surface, a lower surface, and othersof a plug, a wiring, and various types of an insulating film isdescribed as a height or a height position thereof in a directionperpendicular to the main surface of the semiconductor substrate 1S, anda side thereof closer to the main surface of the semiconductor substrate1S is described as a lower side, and a side thereof farther away fromthe main surface of the semiconductor substrate 1S is described as ahigher side.

In the first embodiment, as described later, after the plug PL1 isformed inside the contact hole CNT1 of the interlayer insulating filmPIL, a surface of the insulating film SO, that is, a surface (an uppersurface) of the interlayer insulating film PIL, is made to recede sothat the upper surface of the plug PL1 is higher than the upper surfaceof the insulating film SO, that is, the upper surface of the interlayerinsulating film PL (that is, the upper surface of the interlayerinsulating film PL is lower than the upper surface of the plug PL1).Therefore, in a manufactured semiconductor device, the height of theupper surface of the plug PL1 is higher than the upper surface of theinterlayer insulating film PIL. Therefore, in a wiring W1 to be formedlater than the plug PL1, even if an embedded (buried) amount inside theinsulating film SO, that is, the interlayer insulating film PIL isdecreased, the connection between the plug PL1 and the wiring W1 isensured.

An interlayer insulating film WIL1 is formed on the interlayerinsulating film PIL in which the plug PL is buried, that is, on theinterlayer insulating film PIL and the plug PL1 formed so as to protrudefrom the interlayer insulating film PIL (the insulating film SO).However, a part or whole of the upper surface of the plug PL1 is coveredwith the wiring W1. In the case of FIG. 3, a part of the upper surfaceof the plug PL1 is covered with the wiring W1, and the other partthereof is covered with the interlayer insulating film WIL1. In the caseof FIG. 25 described later, the whole of the upper surface of the plugPL1 is covered with the wiring W1.

The interlayer insulating film WIL1 is formed of a stacked film formedof, for example: an insulating film IL1 formed of a silicon oxide filmas an insulating film; and an insulating film IL2 formed of a SiOC filmwhich is a silicon oxide film containing carbon as a low dielectricconstant film. In the insulating film IL1 and the insulating film IL2forming the interlayer insulating film WIL1, the insulating film IL1 ison a lower-layer side and the insulating film IL2 is on an upper-layerside, and therefore, the insulating film IL2 is formed above theinsulating film

A wiring trench WT1 is formed in the interlayer insulating film WIL1,and the wiring (buried wiring) W1 is formed so as to be buried insidethis wiring trench WT1. The wiring W1 is a buried wiring formed by adamascene technique. A part of the plug PL1 is exposed from the wiringtrench WT1, and the plug PL1 exposed from the wiring trench WT1 is incontact with and is electrically connected to the wiring W1 buried inthe wiring trench WT1. Therefore, the wiring W1 can be regarded as aburied wiring formed inside the interlayer insulating film WIL1, andbesides, a buried wiring connected to the plug PL1.

The reason why the insulating film IL2 is formed of the low dielectricconstant film is that a capacitance (inter-wiring capacitance) betweenadjacent wirings (for example, adjacent wirings W1) is reduced. Also,the insulating film IL1 is an insulating film formed to be sufficientlythinner than the insulating film IL2.

The wiring W1 is formed of a stacked film formed of, for example: abarrier conductor film WBM formed of a tantalum nitride film (a TaNfilm) as a conductive film; and a conductor film CUF formed of a copperfilm (a Cu film) as a conductive film, and is electrically connected tothe plug PL1 formed inside the interlayer insulating film PIL. While thewiring W1 is formed of the barrier conductor film WBM and the conductorfilm CUF as described above, side surfaces and a bottom surface of thewiring W1 are formed of the barrier conductor film WBM, and the otherparts (mainly an inside) thereof are formed of the conductor film CUF.

As described above, a part of the plug PL1 protrudes from the uppersurface of the interlayer insulating film PIL so that the upper surfaceof the plug PL1 is higher than the upper surface of the insulating filmSO, that is, the upper surface of the interlayer insulating film PIL,and therefore, even if the embedded (buried) amount of the wiring W1inside the insulating film SO, that is, the interlayer insulating filmPIL is decreased, the connection between the plug PL1 and the wiring W1can be ensured. Also, since the embedded (buried) amount of the wiringW1 inside the insulating film SO, that is, the interlayer insulatingfilm PIL is decreased, a surface area of a part of the wiring W1 formedinside the insulating film SO, that is, the interlayer insulating filmPIL is decreased, and a surface area of a part of the wiring W1 formedinside the insulating film IL2 which is the low dielectric constant filmis increased. Therefore, the capacitance (inter-wiring capacitance)between the wirings W1 can be reduced.

Note that the delay of the signal transmitted via the wiring can bereduced by the reduction in the inter-wiring capacitance, which furtherresults in the improvement of the electronic performance of thesemiconductor device.

On the interlayer insulating film WIL1 in which a wiring 41 is formed(buried), a second-layer wiring (such as an interlayer insulating filmWIL2, a wiring W2, and a plug PL2, which will be described later) andwiring layers to be formed thereafter are formed. However, illustrationand explanation thereof are omitted here.

The semiconductor device according to the first embodiment is configuredas described above, and a method of manufacturing the same will beexplained below with reference to the drawings.

Each of FIGS. 4 to 23 is a cross-sectional view of a principal part ofthe semiconductor device of the first embodiment in a manufacturingstep. Among them, each of FIGS. 4 to 10 and 19 to 23 illustrates a crosssection corresponding to the cross section A. Also, each of FIGS. 11,17, and 18 illustrates a cross-sectional view in a vicinity of an edgeportion (an end portion) of a wafer (the semiconductor substrate 1S).Further, each of FIGS. 12 to 16 is a cross-sectional view of a principalpart of a semiconductor-element formed portion in FIG. 11 (in thevicinity of the edge portion of the wafer), which corresponds to anexplanatory diagram for a step of forming the contact hole CNT1.

In order to manufacture the semiconductor device of the firstembodiment, as illustrated in FIG. 4, the semiconductor substrate 1Smade of, for example, p⁻-type monocrystalline silicon is prepared first,and the element isolation region STI is formed on the main surface ofthe semiconductor substrate 1S. The element isolation region STI can beformed as, for example, follows.

That is, first, a silicon oxide film (a SiO₂ film) and a silicon nitridefilm (a Si₃N₄ film) are sequentially formed on the semiconductorsubstrate 1S, and this silicon nitride film is etched by using aphotoresist pattern (a patterned photoresist film). Subsequently, byusing this etched silicon nitride film as a mask (an etching mask), atrench (an element isolation trench) is formed in the semiconductorsubstrate 1S. Then, as an insulating film to be buried inside thistrench, for example, a silicon oxide film is deposited on thesemiconductor substrate 1S, the silicon oxide film in an outer region ofthe trench is removed by using a chemical mechanical polishing (CMP)method or others, and the silicon nitride film is further removed by awet etching method. In this manner, the element isolation region STI isformed of an insulating film (an insulator) buried inside the trench.

Next, the p-type well PWL1 is formed in the semiconductor substrate 1S.The p-type well PWL1 can be formed by forming a photoresist pattern (apatterned photoresist film) on the main surface of the semiconductorsubstrate 1S by using a photolithography method, and then,ion-implanting an impurity into the semiconductor substrate 1S by usingthis photoresist pattern as a mask (an ion-implantation blocking mask).At this time, the p-type well PWL1 is formed by implanting ion such asboron (B) as an impurity (p-type impurity) exhibiting a p-typeconductivity. Then, ion implantation (channel-dope ion implantation) ofan impurity for controlling a threshold value of the n-channel-typeMISFET Q₁ may be performed into the p-type well PWL1.

Next, after the surface of the semiconductor substrate 1S is washed(rinsed) by dilute hydrofluoric acid or others, for example, an oxidefilm of silicon (a silicon oxide film) is formed on the main surface(the surface of the p-type well PWL1) of the semiconductor substrate 1Sas an insulating film (an insulating film for a gate insulating film),so that the gate insulating film GI1 is formed as illustrated in FIG. 4.The gate insulating film GI1 can be formed by using, for example, athermal oxidation method. As the gate insulating film GI1, not only thesilicon oxide film but also a silicon oxynitride film (aSi_(x)O_(y)N_(z) film) can be used, or a metal oxide film having ahigher dielectric constant than that of the silicon nitride film, suchas a hafnium oxide film (a Hf₂O₃ film), an aluminum oxide film (an Al₂O₃film), or a tantalum oxide film (a Ta₂O₅ film) may be used.

Next, the gate electrode G1 is formed on the main surface of thesemiconductor substrate 1S (that is, on the gate insulating film GI1).The gate electrode G1 can be formed as, for example, follows.

That is, first, a polycrystalline silicon film to be the gate electrodeG1 later is deposited on the whole main surface of the semiconductorsubstrate 1S. This polycrystalline silicon film can be formed by using,for example, a CVD (Chemical Vapor Deposition) method. Then, thispolycrystalline silicon is etched by using a photoresist pattern (apatterned photoresist film) formed as a mask (an etching mask) by aphotolithography technique, so that the gate electrode G1 is formed ofthe patterned polycrystalline silicon film as illustrated in FIG. 4.

Next, by using a photolithography technique and an ion implantationmethod, the shallow n-type impurity diffusion region EX1 aligned withthe gate electrode G1 is formed inside (the p-type well PWL1 of) thesemiconductor substrate 1S. This shallow low-concentration n-typeimpurity diffusion region EX1 is a semiconductor region (an n-typesemiconductor region) obtained by introducing an n-type impurity such asphosphorus (P) or arsenic (As) into the semiconductor substrate 1S.

Next, as illustrated in FIG. 4, the sidewall (sidewall spacer, sidewallinsulating films) SW1 is formed on both side walls of the gate electrodeG1. The sidewall SW1 can be formed by, for example, forming a siliconoxide film as an insulating film on the semiconductor substrate 1S so asto cover the gate electrode G1, and then, dry-etching (anisotropicallyetching) this silicon oxide film. The sidewall SW1 can be formed of notonly the silicon oxide film but also a silicon nitride film or a stackedfilm formed of a silicon oxide film and a silicon nitride film. Thesidewall SW1 is provided in order to form an LDD (Lightly Doped Drain)structure.

Next, by using a photolithography technique and an ion implantationmethod, the deep n-type impurity diffusion region NR1 aligned with thesidewall SW1 formed on the side walls of the gate electrode G1 is formedinside (the p-type well PWL1 of) the semiconductor substrate 1S asillustrated in FIG. 4. This deep n-type impurity diffusion region NR1 isalso a semiconductor region (an n-type semiconductor region) obtained byintroducing an n-type impurity such as phosphorus (P) or arsenic (As)into the semiconductor substrate 1S. At this time, to the deep n-typeimpurity diffusion region NR1, the n-type impurity with a concentrationhigher than that of the shallow n-type impurity diffusion region EX1 isintroduced. That is, the deep n-type impurity diffusion region NR1 isformed so as to have a higher impurity concentration and a deeperjunction depth than those of the shallow impurity diffusion region EX1.By the shallow n-type impurity diffusion region EX1 and the deep n-typeimpurity diffusion region NR1, the n-type semiconductor region NS1serving as the source region or the drain region of the n-channel-typeMISFET Q₁ is formed.

Next, in order to reduce the resistance value of the gate electrode G1,an upper portion of the gate electrode G1 is reacted to form silicideand form the metal silicide layer NSF1, so that the gate electrode G1has a stacked structure formed of the polycrystalline silicon film andthe metal silicide layer NSF1 thereon as illustrated in FIG. 4.Similarly, in order to reduce the resistance also in the n-typesemiconductor region NS1, the metal silicide layer NSF1 is formed on thesurface of (the deep n-type impurity diffusion region NR1 of) the n-typeimpurity diffusion region NR1. In the first embodiment, a nickelsilicide layer (a NiSi layer) is formed as the metal silicide layerNSF1. The metal silicide layer NSF1 above the gate electrode G1 and themetal silicide layer NSF1 above (the deep n-type impurity diffusionregion NR1 of) the n-type impurity diffusion region NR1 can be formed bya Salicide (Self Aligned Silicide) process in the same step.Hereinafter, the step of forming the metal silicide layer NSF1 will beexplained.

That is, first, for example, a nickel film (a Ni film) is formed on thesemiconductor substrate 1S as a conductive film (a metal film). At thistime, the nickel film is in contact with (the polycrystalline siliconfilm which forms) the gate electrode G1 and a region whose surface isexposed in the n-type impurity diffusion region NR1. Then, a heattreatment is performed to the semiconductor substrate 1S. In thismanner, the nickel film is reacted with a part of (the polycrystallinesilicon film which forms) the gate electrode G1 and (the monocrystallinesilicon which forms) the n-type impurity diffusion region NR1 in contactwith the nickel film, so that the nickel silicide layer is formed. Then,an unreacted nickel film is removed from the semiconductor substrate 1S.Note that the nickel silicide layer is formed as the metal silicidelayer NSF in the first embodiment. However, instead of the nickelsilicide layer, for example, a cobalt silicide layer (a CoSi₂ layer), atitanium silicide layer (a TiSi₂ layer), or a platinum silicide layer (aPtSi layer) may be formed as the metal silicide layer NSF.

As described above, the n-channel-type MISFET Q₁ is formed in thesemiconductor substrate 1S. When the p-channel-type MISFET Q₂ is formed,each polar character (conductive type) of the impurities of the wellregion (the p-type well PWL1) of the above-described n-channel-typeMISFET Q₁, the source region and the drain region (the n-type impuritydiffusion region NR1) thereof, and the gate electrode (the gateelectrode G1) thereof is changed to be opposite thereto.

Next, a wiring step (a step of forming a wiring layer) will beexplained.

As illustrated in FIG. 5, the insulating film SN is formed on thesemiconductor substrate 1S in which the n-channel-type MISFET Q₁ isformed so as to cover the n-channel-type MISFET Q₁. That is, theinsulating film SN is formed on the semiconductor substrate 1S includinga portion on the metal silicide layer NSF1 so as to cover the gateelectrode G1 and the sidewall SW1. The insulating film SN is formed of,for example, a silicon nitride film as an insulating film, and can beformed by using a CVD method. A thickness of the insulating film SN is,for example, 10 nm which is thinner than that of the insulating film SOto be formed later.

Then, the insulating film (the interlayer insulating film) SO is formedon the insulating film SN. The insulating film SO is formed of, forexample, an O₃-TEOS film, a P-TEOS film, or a stacked film formed of theO₃-TEOS film and the P-TEOS film, as an insulating film. The O₃-TEOSfilm is a silicon oxide film which is formed at normal pressure withusing TEOS (Tetraethylorthosilicate) and ozone (O₃) as raw materials,and the P-TEOS film is a silicon oxide film which is formed under plasmawith using TEOS as a raw material. After the insulating film SN and theinsulating film SO are formed, the stacked film formed of the insulatingfilm SN and the insulating film SO is planarized by a CMP method. Athickness of the insulating film SO is, for example, 145 nm. By theinsulating film SN and the insulating film SO, the interlayer insulatingfilm PIL is formed. Since the planarizing process by the CMP method isperformed as described above, an upper surface of the interlayerinsulating film PIL is planarized at this stage.

Next, as illustrated in FIG. 6, the contact hole (through hole, hole)CNT1 is formed in the interlayer insulating film PIL. The contact holeCNT1 can be formed by performing the dry-etching to the interlayerinsulating film PIL by using a photoresist pattern (a patternedphotoresist film) formed on the interlayer insulating film PIL by aphotolithography technique as a mask (an etching mask). The contact holeCNT1 is formed so as to penetrate through the interlayer insulating filmPIL and reach the metal silicide layer NSF1 formed on the n-typeimpurity diffusion region NR1 (the deep impurity diffusion region NR1).Therefore, from a bottom portion of the contact hole CNT1, a part of themetal silicide layer NSF1 formed on the n-type impurity diffusion regionNR1 (the deep impurity diffusion region NR1) is exposed.

When the contact hole CNT1 is formed, dry etching is performed first tothe insulating film SO by using the insulating film SN as an etchingstopper so as to form the contact hole CNT1 in the insulating film SO,and then, the insulating film SN on the bottom portion of the contacthole CNT1 is removed by dry etching, so that the contact hole CNT1penetrating through the interlayer insulating film PIL is formed. Inthis manner, the insulating film SN is formed for so-called SAC (SelfAlign Contact).

Next, as illustrated in FIG. 7, the barrier conductor film PBM is formedon the semiconductor substrate 1S. More specifically, the barrierconductor film PBM is formed on the interlayer insulating film PILincluding an inner wall (the side surfaces and the bottom portion) ofthe contact hole CNT1. In the first embodiment, the barrier conductorfilm PBM is formed of, for example, a stacked film formed of a titaniumfilm (on a lower-layer side) and a titanium nitride film (on anupper-layer side) as a conductor film, and can be formed by using, forexample, a sputtering method. This barrier conductor film PBM is formedin order to prevent diffusion of tungsten to be buried into the siliconoxide film (the insulating film SO) in a later step. The barrierconductor film PBM may be a conductive film having such a function, andmay be formed of, for example, a single layer of a titanium film or atitanium nitride film.

Next, the conductor film TF is formed on the barrier conductor film PBM.The conductor film TF is formed of, for example, a tungsten film (a Wfilm) as a conductor film. The conductor film TF is formed so as to beburied inside the contact hole CNT1, and can be formed by using, forexample, a CVD method.

In this manner, the inside of the contact hole CNT1 is filled with thebarrier conductor film PBM and the conductor film TF, and a plug can beformed in a later step. However, the barrier conductor film PBM and theconductor film TF cannot be formed only inside the contact hole CNT1,and therefore, when these films are formed, the barrier conductor filmPBM and the conductor film TF are formed not only inside the contacthole CNT1 but also on the interlayer insulating film PIL in addition tothe inside of the contact hole CNT1 as illustrated in FIG. 7. Therefore,after the barrier conductor film PBM and the conductor film TF areformed, it is required to remove unnecessary portions of the barrierconductor film PBM and the conductor film TF formed outside the contacthole CNT1 so that the barrier conductor film PBM and the conductor filmTF remain only inside the contact hole CNT1 as described later.

Next, as illustrated in FIG. 8, the unnecessary portions of theconductor film TF and the barrier conductor film PBM formed outside thecontact hole CNT1 are removed by a CMP method. In this manner, (an uppersurface) of the insulating film SO is exposed, and the plug PL1 isformed inside the interlayer insulating film PIL (more specifically,inside the contact hole CNT1). The plug PL1 is formed of the barrierconductor film PBM and the conductor film TF which are buried and remaininside the contact hole CNT1.

In the first embodiment, the interlayer insulating film PIL is formed ofthe insulating film SN and the insulating film SO formed on theinsulating film SN. Thus, in the first embodiment, the upper surface ofthe interlayer insulating film PIL is namely the upper surface of theinsulating film SO. Therefore, in the following steps, the upper surfaceof the insulating film SO is used synonymously with the upper surface ofthe interlayer insulating film PIL. Also, the inside of the insulatingfilm SO is used synonymously with the inside of the interlayerinsulating film PIL.

Next, as illustrated in FIG. 9, by making the upper surface of theinsulating film SO to recede by etching, the upper surface of theinsulating film SO is made lower than the upper surface of the plug PL1.That is, the upper surface of the insulating film SO is made to recedeso that the upper surface of the insulating film SO is lower than theupper surface of the plug PL1. In this manner, a part of the plug PL1 isprotruded from the upper surface of the insulating film SO. For example,by making the upper surface of the insulating film SO to recede by 25 nmby etching, the upper surface of the insulating film SO is made lowerthan the upper surface of the plug PL1 by 25 nm, so that the plug PL1 isprotruded by 25 nm from the upper surface of the insulating film SO.Note that the recession of the upper surface of the insulating film SOcorresponds to the thinning of the insulating film SO so that the heightposition of the upper surface of the insulating film SO is lowered.

Since the insulating film SO is etched in this step (the stepillustrated in FIG. 9), a thickness of the insulating film SO in FIG. 9is thinner by, for example, 25 nm, than a thickness of the insulatingfilm SO obtained at the planarization period in the step illustrated inFIG. 5 described above. However, if the thickness of the insulating filmSO formed above the n-channel-type MISFET Q₁ is too thin, there is apossibility of reduction in reliability between the wiring W1 to beformed in a later step and the gate electrode G1 of the n-channel-typeMISFET Therefore, it is required to set the thickness of the insulatingfilm SO formed in the step illustrated in FIG. 5 described above and anetching amount of the insulating film SO in this step (the stepillustrated in FIG. 9) so as to ensure a desired thickness capable ofensuring the reliability between the wiring W1 to be formed in a laterstep and the gate electrode G1 of the n-channel-type MISFET Q₁ as thethickness of the insulating film SO obtained at the stage of FIG. 9.

Also, the etching of this step (the step illustrated in FIG. 9) can beeither of dry etching and wet etching as long as the insulating film SOcan be selectively etched with respect to the conductive film TF (theplug PL1). That is, for the step illustrated in FIG. 9 (the step ofmaking the upper surface of the insulating film SO to recede), etchingwith selectivity for the insulating film SO can be used, that is,etching under an etching condition which allows the insulating film SOto be etched easier than the plug PL1 (in other words, an etchingcondition which allows an etching speed of the insulating film SO to behigher than an etching speed of the plug PL1) can be used.

In the first embodiment, after the unnecessary portions of the conductorfilm TF and the barrier conductor film PBM are removed by using the CMPmethod, the upper surface of the insulating film SO is made to recede bythe etching (that is, the height position of the upper surface of theinsulating film SO is made lower by the etching), so that the uppersurface of the plug PL1 is made higher than the upper surface of theinsulating film SO. However, the method is not limited to such a method.By optimizing a polishing liquid used in the CMP method, the CMP methodcan be used all from the step of removing the conductor film TF and thebarrier conductor film PBM formed outside the contact hole GNT1 to thestep of making the upper surface of the insulating film SO to recede. Inthis case, the CMP method with the selectivity for the insulating filmSO can be used in the step illustrated in FIG. 9 (the step of making theupper surface of the insulating film SO to recede).

For example, the polishing (removal) of the conductor film TF and thebarrier conductor film PBM formed outside the contact hole GNT1 and therecession of (the upper surface of) the insulating film SO can beperformed by using one type of the polishing liquid (CMP polishingliquid). In this case, a polishing liquid is used, the polishing liquidhaving a higher selectivity for the insulating film SO, that is, thepolishing liquid having a higher polishing speed for the insulating filmSO than that for the conductor film TF and the barrier conductor filmPBM. When the polishing is performed by the CMP method with using thispolishing liquid, the polishing amount of the insulating film SO becomeslarger than the polishing amounts of the conductor film TF and thebarrier conductor film PBM after the conductor film TF and the barrierconductor film PBM formed outside the contact hole CNT1 are removed bythe polishing so as to expose the insulating film SO, and therefore, theinsulating film SO can be made to recede (by, for example, 25 nm) fromthe upper surface of the plug PL1 as illustrated in FIG. 9. When thismethod is adopted, the above-described dry etching step is not required,and therefore, there is a merit that the steps can be simplified.

In the forming method described above, the step of polishing theconductor film TF to the step of making the insulating film SO to recedeafter the insulating film SO is exposed are performed with one type ofthe polishing liquid. However, the polishing is not limited to the CMPmethod with one type of the polishing liquid as described above, and ispossible with two types of polishing liquids. For example, the polishingby the CMP method is performed with the polishing liquid having the highselectivity for the conductor film TF and the barrier conductor filmPBM, that is, the polishing liquid having the higher polishing speed forthe conductor film TF and the barrier conductor film PBM than that forthe insulating film SO until the conductor film TF and the barrierconductor film PBM formed outside the contact hole CNT1 are polished soas to expose the insulating film SO. And, after the conductor film TFand the barrier conductor film PBM formed outside the contact hole CNT1are removed by the polishing so as to expose the insulating film SO, thepolishing by the CMP method is performed with the polishing liquidhaving the higher selectivity for the insulating film SO, that is, thepolishing liquid having the higher polishing speed for the insulatingfilm SO than those for the conductor film TF and the barrier conductorfilm PBM. In this manner, when the conductor film TF and the barrierconductor film PBM formed outside the contact hole CNT1 are polished, byusing the polishing liquid having the higher selectivity for theconductor film TF and the barrier conductor film PBM, the time forpolishing the conductor film TF and the barrier conductor film PBMrequired to expose the insulating film SO can be shortened. In the CMPmethod with the two types of polishing liquids, the polishing can beperformed by using the same apparatus, or, different apparatuses can beused for the respective polishing liquids.

Next, the first-layer wiring is formed by a single damascene method.Hereinafter, a method of forming the first-layer wiring will beexplained.

First, as illustrated in FIG. 10, the insulating film IL1 is formed onthe interlayer insulating film PIL (including a portion on the plugPL1). The insulating film IL1 is formed on the interlayer insulatingfilm PIL so as to cover a portion of the plug PL1 protruding from theupper surface of the interlayer insulating film PIL. Then, theinsulating film IL2 is formed on the insulating film IL1. The insulatingfilm IL1 is formed so as to be thinner than the insulating film IL2. Athickness of the insulating film IL1 is, for example, 15 nm, and athickness of the insulating film IL2 is, for example, 70 nm. By theseinsulating film IL1 and insulating film IL2, the interlayer insulatingfilm WIL1 of the first-layer wiring is formed.

Here, the insulating film IL2 is formed of a SiOC film which is a filmformed by, for example, adding carbon (C) to a silicon oxide film (thatis, a silicon oxide film containing carbon) as a low dielectric constantfilm. The insulating film IL2 is formed of the low dielectric constantfilm in order to reduce the inter-wiring capacitance of wirings to beformed in a later step. Note that the low dielectric constant film canbe exemplified by an insulating film having a dielectric constant lowerthan a dielectric constant of a silicon oxide film, and generally refersto a low dielectric constant film having a dielectric constant of thesilicon oxide film which is about “ε=4.1 to 4.2” or lower. Therefore,the insulating film IL2 formed as the low dielectric constant film has adielectric constant lower than that of silicon oxide. Also, theinsulating film IL2 has a dielectric constant lower than those of theinsulating films SO and IL1. While the insulating film IL2 is the lowdielectric constant film, not only a SiOC film (k˜2.2) but also a SiOFfilm (k˜3.7), an ULK film (k˜2.7), an ELK film (k˜2.2), a spin-coatedporous MSQ film (k˜2.2), or a stacked film thereof can be used.

In the first embodiment, the interlayer insulating film WIL1 is formedof a stacked film formed of the insulating film IL1 and the insulatingfilm IL2 thereon. This is because of the following reason.

That is, in the step illustrated in FIG. 6, when the contact hole CNT1is formed inside the interlayer insulating film PIL, a lower-layermaterial LM and a middle layer ML are used in the first embodiment asillustrated in FIG. 11 in addition to an upper-layer resist film (aphotoresist film) UR used in a normal step. FIG. 11 is a cross-sectionalview of a principal part in a vicinity of an edge portion of the wafer(the semiconductor substrate 1S), obtained when the step illustrated inFIG. 5 ends, and then, the lower-layer material LM, the middle layer ML,and the upper-layer resist film UR are formed on the wafer (thesemiconductor substrate 1S).

With reference to FIGS. 12 to 16, details of the step of etching theinterlayer insulating film PIL upon the formation of the contact holeCNT1 will be explained. Note that, while FIGS. 12 to 16 are explanatorydiagrams of the step of forming the contact hole CNT1, FIG. 12corresponds to a partially-enlarged cross-sectional view illustrating toenlarge a region where a semiconductor element (a MISFET) is formed inFIG. 11, and each of FIGS. 13 to 16 illustrates the same region as thatin FIG. 12. For simplification, in FIGS. 12 to 16, the illustration ofthe semiconductor element (MISFET) is omitted, and the insulating filmSN and the insulating film SO are collectively illustrated as theinterlayer insulating film PIL.

First, as illustrated in FIG. 12, for example, a low-sublimation organicfilm is formed on the interlayer insulating film PIL so as to have athickness of, for example, 180 nm, as the lower-layer material LM. Onthe lower-layer material LM, for example, an organic film containingsilicon (Si) and carbon (C) as main components is formed as the middlelayer ML so as to have a thickness of, for example, 40 nm, which isthinner than the interlayer insulating film PIL and the lower-layermaterial LM. Further, on the middle layer ML, the upper-layer resistfilm UR is formed so as to have a thickness of, for example, 150 nm.Next, by a lithography technique by using a mask (an exposure mask),exposure and development are performed to the upper-layer resist film URso as to form a through hole TH1 in the upper-layer resist film UR. Notethat a state of the above-described FIG. 11 corresponds to a stage afterthe formation of the lower-layer material LM, the middle layer ML, andthe upper-layer resist film UR but before the formation of the throughhole TH1 in the upper-layer resist film UR.

Next, as illustrated in FIG. 13, the middle layer ML is etched by usingthe patterned upper-layer resist film UR (that is, the upper-layerresist film UR having the through hole TH1 formed therein) as a mask (anetching mask), so that a through hole TH2 is formed in the middle layerML. At this time, a diameter of an upper surface of the through hole TH2formed in the middle layer ML is almost equal to a diameter of thethrough hole TH1 (that is, the through hole TH2 is formed so that theupper surface thereof is aligned with a lower surface of the throughhole TH1). On the other hand, a diameter of a lower surface of thethrough hole TH2 is smaller than a diameter of the through hole TH1.That is, the through hole TH2 is formed in a tapered shape whoselower-potion diameter is narrower (smaller) than an upper-portiondiameter thereof.

Next, as illustrated in FIG. 14, the lower-layer material LM is etchedby using the middle layer ML patterned in the step illustrated in FIG.13 (that is, the middle layer ML having the through hole TH2 formedtherein) as a mask (an etching mask), so that a through hole TH3 isformed in the lower-layer material LM. At this time, a diameter of thethrough hole TH3 formed in the lower-layer material LM is almost equalto a diameter of a lower surface of the through hole TH2 (that is, thethrough hole TH3 is formed so as to be aligned with an upper surfacethereof with the lower surface of the through hole TH2).

Next, as illustrated in FIG. 15, the interlayer insulating film PIL isetched by using the lower-layer material LM patterned in the stepillustrated in FIG. 14 (that is, the lower-layer material LM having thethrough hole TH3 formed therein) and the middle layer ML remaining afterthe etching in the step illustrated in FIG. 14 as masks (etching masks),so that the contact hole CNT1 in the interlayer insulating film PIL. Atthis time, a diameter of an upper surface of the contact hole CNT1formed in the interlayer insulating film PIL is almost equal to adiameter of a lower surface of the through hole TH3 (that is, thecontact hole CNT1 is formed so as to be aligned with an upper surfacethereof with a lower surface of the through hole TH3). Finally, thelower-layer material LM is removed as illustrated in FIG. 16.

When a fine pattern is formed, it is required to thin the resist film inorder to maintain resolution of the resist film (the photoresist film).However, in the thin resist film, there is a problem of insufficientetching resistance of the resist film for a film to be processed (a filmto be processed by using the resist pattern as the etching mask).Accordingly, as described above (as explained with reference to theabove-described FIGS. 12 to 16), by patterning the respective films (theupper-layer resist film UR, the middle layer ML, the lower-layermaterial LM, and the interlayer insulating film PIL), the etchingresistance at each patterning stage of the respective films can beensured even if the resist film (the upper-layer resist film UR) isthinned in order to maintain the resolution. More particularly, sincethe middle layer ML to be patterned by using the upper-layer resist filmUR is formed thinner than the lower-layer material LM, the upper-layerresist film UR can be formed thin. Further, as described above, sincethe through hole TH2 to be formed by patterning the middle layer ML isformed in the tapered shape whose lower-portion diameter is smaller thanthe upper-portion diameter thereof, the diameter of the through hole TH3in the lower-layer material LM etched by using the patterned middlelayer ML as the mask (etching mask) is formed so as to be almost equalto the diameter of the lower surface of the through hole TH2, so thatthe contact hole CNT1 having the smaller diameter than the diameter ofthe through hole TH1 formed in the upper-layer resist film UR can beformed.

However, when the contact hole CNT1 is formed in the interlayerinsulating film PIL by using the method as described above (theabove-described FIGS. 12 to 16), the middle layer ML is formed thick atan edge portion (an end portion) of the wafer (the semiconductorsubstrate 1S) as illustrated in FIG. 11 described above. Therefore, asillustrated in FIG. 16, even after the contact hole CNT1 is formed andafter the lower-layer material LM remaining in the region where thesemiconductor element is to be formed is removed, the middle layer ML isnot removed and remains at the edge portion of the wafer. Then, the stepof forming the plug PL1 by burying the conductive film in the contacthole CNT1 is performed. Even after this step is performed, the middlelayer ML remains at the edge portion of the wafer as illustrated in FIG.17. The edge portion of the wafer has a weak film adhesiveness, andtherefore, if the film of the middle layer ML partially remains, thereis a risk that the remaining film (the middle layer ML remaining at thewafer edge portion) is peeled off in a later step and reattaches to thewafer, which results in decrease in a yield. Therefore, as illustratedin FIG. 18, it is required to remove the middle layer ML remaining atthe edge portion of the wafer by etching or polishing. At this time,simultaneously with the removal of the partially-remaining middle layerML, the interlayer insulating film PIL formed at the edge portion of thewafer is also removed, and therefore, the surface of the wafer isexposed from the edge portion of the wafer as illustrated in FIG. 18. Inthis manner, there is a new risk of occurrence of the following problem.

After the plug PL1 is formed, it is originally sufficient to form theinsulating film IL2 which is the low dielectric constant film on theinterlayer insulating film PIL. However, since the SiOC film formed asthe insulating film IL2 in the first embodiment is formed under unusualplasma discharge, there is a risk that abnormal electrical dischargeoccurs if the film is formed in the state that the surface of the waferis exposed, which results in damage of the wafer (semiconductorsubstrate 1S). Therefore, in the first embodiment, it is desired to formthe insulating film IL1 so as to cover the surface of the semiconductorsubstrate 1S after the surface of the semiconductor substrate 1S isexposed by the etching for removing the middle layer ML remaining at theedge portion of the wafer but before the insulating film IL2 is formed.In this manner, the SiOC film can be formed as the insulating film IL2in a state that the surface of the wafer (the semiconductor substrate1S) is not exposed, and therefore, the damage of the wafer (thesemiconductor substrate 1S) upon the formation of the SiOC film (theinsulating film IL2) can be prevented. As the insulating film IL1 forcovering the semiconductor substrate 1S, an insulating film such as asilicon oxide film or a silicon nitride film can be considered. Since awiring trench (corresponding to the wiring trench WT1 which will bedescribed later) to be formed in a later step is also formed inside theinsulating film IL1, it is desired to avoid the formation of theinsulating film IL1 formed by using a high dielectric constant filmwhich leads to the increase in the inter-wiring capacitance. In thefirst embodiment, the silicon oxide film is preferably used as theinsulating film IL1.

In the first embodiment, because of the above-described reason, theinterlayer insulating film WIL1 is formed so as to have the stackedstructure formed of the insulating film IL1 and the insulating film IL2.However, the case that the insulating film IL1 is changed to the stackedstructure formed of the insulating film IL1 and the insulating film IL2is not limited to the above-described reason. For example, a case can bealso considered, the case forming the insulating film IL1 as an etchingstopper upon the formation of the wiring trench (corresponding to thewiring trench WT1 which will be described later) inside the interlayerinsulating film WIL1 in a later step. Also in this case, as theinsulating film IL1, for example, an insulating film such as a siliconoxide film, a silicon nitride film, a silicon carbide film (a SiC film),a silicon carbonitride film (a SiCN film), or a silicon oxynitride film(a SiON film) can be considered. However, it is required to avoid usageof a film having a function of the etching stopper for a low dielectricconstant film, and besides, having a high dielectric constant whichresults in the increase in the inter-wiring capacitance. On the otherhand, when the above-described abnormal electrical discharge does notoccur or when the etching stopper is not required, the interlayerinsulating film WIL1 can be formed of one layer of the insulating filmIL2 without forming the insulating film IL1.

Next (that is, after the interlayer insulating film WIL1 is formed asillustrated in the above-described FIG. 10), the wiring trench WT1 isformed in the interlayer insulating film WIL1 as illustrated in FIG. 19.At this time, the wiring trench WT1 is formed so that at least a part ofthe upper surface of the plug PL1 overlaps the wiring trench WT1 inplane, and therefore, a part of the plug PL1 is exposed because of thewiring trench WT1.

In the first embodiment, as illustrated in the above-described FIG. 2,the step of manufacturing the semiconductor device in the case that thewhole wiring W1 is slightly shifted from the plug PL1 in a directionparallel to the cross section A is explained. Therefore, the wiringtrench WT1 formed in the step illustrated in FIG. 19 is also formed soas to be slightly shifted from the plug PL1 in the direction parallel tothe cross section A. A depth of the wiring trench WT1 is, for example,90 nm.

As illustrated in FIG. 19, in the first embodiment, at least a part ofan upper surface (an upper portion) of the plug PL1 and a part of sidesurfaces thereof are exposed because of the wiring trench WT1. Also,while the wiring trench WT1 is formed in the interlayer insulating filmWIL1, a lowermost surface thereof is formed inside the insulating filmSO. That is, the wiring trench WT1 is formed inside the interlayerinsulating film WIL1 and the insulating film SO. The lowermost surfaceof the wiring trench WT1 is at a position lower than the upper surfaceof the plug PL1, and, in the first embodiment, the wiring trench WT1 isformed so that the lowermost surface of the wiring trench WT1 ispositioned lower than (on a lower side of) the upper surface of theinsulating film SO. The height of the lowermost surface of the wiringtrench WT1 is lower than the height of the upper surface of theinsulating film SO, and, for example, the lowermost surface of thewiring trench WT1 is positioned at a position 5 nm lower than the uppersurface of the insulating film SO. In the first embodiment, thelowermost surface of the wiring trench WT1 is formed inside theinsulating film SO, and therefore, the lowermost surface of the wiringtrench WT1 is formed of an exposed surface of the insulating film SO.

Note that the lower surface (the bottom surface) of a portion of thewiring trench WT1 not overlapping the plug PL1 in the plane forms thelowermost surface of the wiring trench WT1, and this manner is commonamong the present first embodiment and the following second to seventhembodiments.

In the first embodiment, since the upper surface of the insulating filmSO is made to recede in the step illustrated in the above-described FIG.9, the upper surface of the plug PL1 is formed at a position higher thanthe upper surface of the insulating film SO. Further, the lowermostsurface of the wiring trench WT1 is formed inside the insulating filmSO. Therefore, the lowermost surface of the wiring trench WT1 is formedat a position lower than the upper surface of the plug PL1. Therefore,at least a part of the upper surface of the plug PL1 and a part of theside surfaces of the plug PL1 are exposed because of the wiring trenchWT1. When a conductive film is buried inside the wiring trench WT1 in alater step, the plug PL1 and the conductive film buried inside thewiring trench WT1 are reliably connected to each other.

In order to form the wiring trench WT1, the interlayer insulating filmWIL1 and the insulating film SO are dry-etched by using a photoresistpattern (a patterned photoresist film) formed on the interlayerinsulating film WIL1 by photolithography technique as a mask (an etchingmask). In this etching step, an endpoint of the insulating film IL2 inthe dry etching is detected. This endpoint detection is observed in, forexample, a scribe region.

More specifically, in the step of forming the wiring trench WT1, theinsulating film IL2 is dry-etched first. At the time when a part of thesurface of the insulating film IL1 is exposed, the endpoint of theinsulating film IL2 in the dry etching is detected. In the present firstembodiment, the insulating film IL2 is formed of the SiOC film, and theinsulating film IL1 is formed of the silicon oxide film. In this manner,the insulating film IL2 and the insulating film IL1 are formed ofdifferent materials (material films) from each other, and therefore, thereflected-light intensity of the insulating film during being etched,the mass of the substance of the same, or others is analyzed at the timewhen the etching reaches a boundary (an interface) between the twoinsulating films IL1 and IL2, so that the endpoint of the insulatingfilm IL2 in the etching can be detected. In the present firstembodiment, after the endpoint of the insulating film IL2 in the etchingis detected, the insulating film IL1 and the insulating film SO arefurther dry-etched. Since the endpoint of this dry etching is inside theinsulating film SO, the endpoint cannot be detected, and therefore, theetching is performed for a predetermined period of time (a certain time)by controlling etching time. A dry-etching (etching-thickness) amount ofeach of the insulating film IL1 and the insulating film SO is smallerthan a dry-etching (etching-thickness) amount of the insulating filmIL2. Therefore, even if the etching endpoint is not detected upon thedry etching of the insulating film IL1 and the insulating film SO,variation in the etching amount (etching thickness) is not large.Therefore, it is possible to avoid the formation of the lowermostsurface of the wiring trench WT1 at a position close to the gateelectrode G1 of the n-channel-type MISFET Q₁ due to theexcessively-large etching amount of the insulating film SO in the stepof forming the wiring trench WT1.

Therefore, the step of forming the wiring trench WT1 includes: a firststep of etching the insulating film IL2; a second step of detecting theetching endpoint of the insulating film IL2 when the etching in thefirst step reaches the upper surface of the insulating film IL1; and athird step of etching the insulating film IL1 and the insulating film SOafter the second step.

As described above, by performing the dry etching (dry etching forforming the wiring trench WT1) in two stages (the first step and thethird step), processing accuracy of the etching can be improved. Also,by the above-described etching (dry etching for forming the wiringtrench WT1), at least a part of the upper surface of the plug PL1 and apart of the side surfaces of the same are exposed because of the wiringtrench WT1. However, the insulating film IL1 may remain on the sidesurfaces of the plug PL1 in some cases. In this case, it is preferred toperform wet etching or others after the dry etching for forming thewiring trench WT1 so as to remove the insulating film IL1 remaining onthe side surfaces of the plug PL1 and expose the side surfaces of theplug PL1 from the wiring trench WT1. In this manner, the reliableconnection between a wiring (corresponding to the wiring W1 which willbe described later) to be formed in a later step and the plug PL1 can beensured.

Next, as illustrated in FIG. 20, a barrier conductor film WBM is formedon the interlayer insulating film WIL1 including an inner wall (sidesurfaces and a bottom portion) of the wiring trench WT1. In the presentfirst embodiment, the barrier conductor film WBM is formed of a stackedfilm formed of a tantalum film (a Ta film) and a tantalum nitride film(a TaN film) thereon, and can be formed by using, for example, asputtering method. A thickness of the barrier conductor film WBM is, forexample, 10 nm. This barrier conductor film WBM is formed in order toachieve adhesiveness with a copper film (a Cu film) to be formed in alater step and to prevent diffusion of the copper. The formation of thestacked film formed of the tantalum film and the tantalum nitride filmis exemplified as the barrier conductor film WBM in the present firstembodiment. However, the barrier conductor film WBM can be formed of asingle layer of a metal film made of tantalum (Ta) or others, a singlelayer of a nitride film (a metal nitride film) such as a titaniumnitride film, or a stacked film formed of a metal film and a nitridefilm (a metal nitride film). When the barrier conductor film WBM is atantalum film or a tantalum nitride film, adhesiveness to a copper filmis excellent compared with the case of using a titanium nitride film.

Next, as illustrated in FIG. 20, a conductor film CUF is formed on thebarrier conductor film WBM. The conductor film CUF is formed of, forexample, a copper film (a Cu film) as a conductor film. This step can beperformed by forming a copper seed layer (not illustrated) on thebarrier conductor film WBM by, for example, a CVD method or a sputteringmethod, and further forming the conductor film CUF on the seed layer by,for example, an electrolytic-plating method. The conductor film CUF isformed thicker than the barrier conductor film WBM, and besides, isformed so as to be buried (fill) inside the wiring trench WT1. In thismanner, the barrier conductor film WBM and the conductor film CUF areburied inside the wiring trench WT1.

However, the barrier conductor film WBM and the conductor film CUFcannot be formed only inside the wiring trench WT1. Therefore, upon theformation of these films, as illustrated in FIG. 20, the barrierconductor film WBM and the conductor film CUF are formed not only insidethe wiring trench WT1 but also on the interlayer insulating film WIL1 inaddition to the inside of the wiring trench WT1.

Next, as illustrated in FIG. 21A, unnecessary portions of the conductorfilm CUF and the barrier conductor film WBM formed outside the wiringtrench WT1 are polished by using a CMP method. In this manner, theconductor film CUF and the barrier conductor film WBM formed outside thewiring trench WT1 are removed, so that the wiring W1 of the first-layerwiring is formed. The wiring W1 is formed of the conductor film CUF andthe barrier conductor film WBM buried and remaining inside the wiringtrench WT1, and a depth of the wiring W1 is similar to that of thewiring trench WT1, which is, for example, 90 nm. The wiring W1 is buriedin the wiring trench WT1, and is a so-called buried wiring (a damascenewiring, a single damascene wiring). The wiring W1 buried in the wiringtrench WT1 is connected to the plug PL1 exposed from the wiring trenchWT1.

Since the wiring trench WT1 is formed inside the interlayer insulatingfilm WIL1 and the insulating film SO in the present first embodiment,the lowermost surface of the wiring W1 which is formed by burying thebarrier conductor film WBM and the conductor film CUF inside the wiringtrench WT1 is formed inside the insulating film SO. Since the lowermostsurface of the wiring W1 is formed inside the insulating film SO, thelowermost surface of the wiring W1 is in contact with the exposedsurface of the insulating film SO.

Note that the lower surface (the bottom surface) of a portion of thewiring W1 not overlapping the plug PL1 in the plane forms the lowermostsurface of the wiring W1, and this is common among the first presentembodiment and the following second to seventh embodiments.

The lowermost surface of the wiring W1 is at a position lower than theupper surface of the plug PL1, and the lowermost surface of the wiringW1 is positioned lower than (on a lower side of) the upper surface ofthe insulating film SO in the first embodiment. The height position ofthe lowermost surface of the wiring W1 is equal to the height positionof the lowermost surface of the wiring trench WT1 in which the wiring W1is buried, and is at a position, for example, 5 nm lower than the uppersurface of the insulating film SO. Also, the upper surface of the plugPL1 is formed at a position higher than the upper surface of theinsulating film SO, and besides, the lowermost surface of the wiring W1is formed at a position lower than the upper surface of the plug PL1,and therefore, at least a part of the upper surface of the plug PL1 anda part of the side surfaces of the same (that is, the exposed portion ofthe plug PL1 from the wiring trench WT1) are covered with the wiring W1.In this manner, the connection between the plug PL1 and the wiring W1can be ensured, and reliability of the connection between the plug PL1and the wiring W1 can be improved. In FIG. 21A, a length (a distance) ofa portion where the plug PL1 and the wiring W1 overlap with each otherin a direction perpendicular to the semiconductor device 1S is indicatedas a length L1. This length L1 is also a distance from the lower surfaceof the wiring W1 (more specifically, the lowermost surface of the wiringW1) to the upper surface of the plug PL1. The length L1 is, for example,30 nm.

FIG. 21B is a cross-sectional view of a principal part of asemiconductor device of the first embodiment as a first comparativeexample, and illustrates a case that a plug PL101, a wiring trenchWT101, and a wiring W101 are formed as different from the firstembodiment but as in the manufacturing step of the comparative exampleexplained with reference to the above-described FIGS. 60 to 65.

FIG. 21B illustrates a case that each member is formed so that theheight of the plug PL101 and the heights of the upper surfaces of thewiring W101 and the interlayer insulating film WIL1 obtained after thewiring W101 is formed are equal to the height of the plug PL1 and theheights of the upper surfaces of the wiring W1 and the interlayerinsulating film WIL1 obtained after the wiring W1 is formed,respectively. That is, in FIG. 21B, a length L101 of a portion where theplug PL101 and the wiring W101 overlap with each other in the directionperpendicular to the semiconductor substrate 1S is set to be almostequal to the above-described length L1 in FIG. 21A (that is, “L1=L101”).

In each step performed in the first embodiment, there are variations inthe polishing amount, the etching amount, and others, and therefore, inorder to ensure the connection between the wiring W1 and the plug PL1even if there is variation in each step, it is desired that the wiringW1 and the plug PL1 are designed so that they overlap with each other bya predetermined length in the direction perpendicular to thesemiconductor substrate 1S. In the first embodiment, this length is setto be the length L1.

In the manufacturing step of the comparative example explained withreference to the above-described FIGS. 60 to 65, the height of the uppersurface of the plug PL101 illustrated in FIG. 21B tends to be formed tobe equal to that of the upper surface of the insulating film SO or lowerthan that of the upper surface of the insulating film SO. Therefore, inthe first comparative example illustrated in FIG. 21B, in order toensure the length L101 of the portion where the wiring W101 and the plugPL101 overlap with each other in the direction perpendicular to thesemiconductor device 1S, the wiring W101 is formed so as to be embedded(buried) inside the insulating film SO by the length L101. In this case,a ratio of a portion of the wiring W101 which is formed inside theinsulating film IL2 which is the low dielectric constant film is small,and therefore, there is a problem that the inter-wiring capacitancecannot be effectively reduced in spite of the fact that most portion ofthe interlayer insulating film WIL1 is formed of the insulating film IL2which is the low dielectric constant film.

On the other hand, in the manufacturing step of the first embodiment,after the polishing for forming the plug PL1 is performed, the uppersurface of the insulating film SO is made to recede, so that the uppersurface of the insulating film SO is formed at a position lower than theupper surface of the plug PL1. Therefore, even if the plug PL1 and thewiring W1 are overlapped with each other by the length L1 in thedirection perpendicular to the semiconductor substrate 1S as illustratedin FIG. 21A, it is not required to form the wiring W1 so as to beembedded (buried) inside the insulating film SO deeper than that in thecase of the manufacturing step of the above-described comparativeexample. Therefore, in the first embodiment, the ratio of the portion ofthe wiring W1 which is formed inside the insulating film IL2 which isthe low dielectric constant film can be larger than that that in thecase of the manufacturing step of the above-described comparativeexample, and therefore, the surface area of the wiring W1 inside theinsulating film IL2 is increased, so that the inter-wiring capacitancecan be effectively reduced.

Also, in the manufacturing step of the above-described comparativeexample, by embedding (burying) the wiring trench WT101 by the lengthL101 from the upper surface of the insulating film SO, it is required toensure the length L101 of the portion where the wiring W101 and the plugPL101 to be formed later overlap with each other in the directionperpendicular to the semiconductor substrate 1S. If the microfabricationof wirings is developed, it is desired to decrease this length L101 inaccordance with that. However, if the length L101 is decreased in acurrent processing accuracy of each step, it becomes difficult to ensurethe reliability of the connection between the wiring W101 and the plugPL101. That is, this means that, even if the microfabrication of thewiring W101 is achieved, it is required in the manufacturing step of theabove-described comparative example to form the wiring W101 so as to beembedded (buried) inside the insulating film SO by the length L101 inorder to ensure the connection between the wiring W101 and the plugPL101. Therefore, due to the microfabrication of wirings, the ratio ofthe portion of the wiring W101 which is formed inside the insulatingfilm IL2 which is the low dielectric constant film is further decreased.This means that, if the microfabrication is achieved in themanufacturing step of the above-described comparative example, theinter-wiring capacitance is further increased.

However, in the first embodiment, by forming the upper surface of theplug PL1 so as to be higher than the upper surface of the insulatingfilm SO, the wiring W1 can be formed so as not to be embedded (buried)inside the insulating film SO deeper than that in the manufacturing stepof the above-described comparative example even if the length L1 of theportion where the wiring W1 and the plug PL1 overlap with each other inthe direction perpendicular to the semiconductor substrate 1S isensured. Therefore, in the first embodiment, even if themicrofabrication of wirings is achieved, the increase in theinter-wiring capacitance between the wirings W1 due to the large ratioof the portion of the wiring W1 which is formed inside the insulatingfilm SO can be avoided compared with the manufacturing step of theabove-described comparative example.

Also, by avoiding the formation of the lowermost surface of the wiringtrench WT1 at the position close to the gate electrode G1 of there-channel-type MISFET Q₁, it can be avoided to decrease the distancebetween the wiring W1 and the gate electrode G1, and it can be avoidedto reduce the reliability between the wiring W1 and the gate electrodeG1. In the first embodiment, the case that the insulating film IL2 isformed of the low dielectric constant film is exemplified. However,regarding the effect of avoiding the reduction in the reliabilitybetween the wiring W1 and the gate electrode G1, it is not alwaysrequired to form the insulating film IL2 by the low dielectric constantfilm. In this case, the insulating film IL2 can be formed of, forexample, a silicon oxide film as the insulating film.

In the first embodiment, the above-described effect can be obtained byforming the upper surface of the plug PL1 so as to be even slightlyhigher than the upper surface of the insulating film SO. Here, a morepreferable condition used when the wiring W1 is formed for the plug PL1will be explained.

FIG. 22 is an enlarged cross-sectional view of a principal part (apartially-enlarged cross-sectional view) of an enlarged periphery of aregion where the plug PL1 and the wiring W1 are connected to each otherin FIG. 21A. Hereinafter, with reference to FIG. 22, a more preferablecondition for the formation of the plug PL1 and the wiring W1 will beexplained. Note that each of the above-described length L1, lengths L1a, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, and L12, which will bedescribed later, and distances L1 b and L1 c, which will be describedlater, indicates a distance (a difference in height, a differencebetween height positions) in a direction (a height direction)perpendicular to the main surface of the semiconductor device 1S.

As illustrated in FIG. 22, a distance (a length) from the upper surfaceof the insulating film SO to the upper surface of the plug PL1 is set asthe length L2. That is, a distance (a length) of protrusion of the plugPL1 from the position of the upper surface of the insulating film SO isset as the length L2. Meanwhile, a distance (a length) from thelowermost surface of the wiring W1 to the upper surface of theinsulating film SO is set as the length L3. That is, a distance of theembedding (burying) of the wiring W1 from the position of the uppersurface of the insulating film SO is set as the length L3. Here, in thefirst embodiment, addition of the length L2 and the length L3corresponds to the above-described length L1 (that is, “L1=L2+L3”). Notethat, for easily understand, in FIG. 22, an upper surface of theinsulating film SO is provided with a reference symbol SOSF so as to berepresented as the upper surface SOSF of the insulating film SO, anupper surface of the plug PL1 is provided with a reference symbol PLSFso as to be represented as the upper surface PLSF of the plug PL1, andthe lowermost surface of the wiring W1 is provided with a referencesymbol W1SF so as to be represented as the lowermost surface W1SF of thewiring W1.

At this time, in the first embodiment, it is desired that a relation of“L2>L3” is established between the length L2 and the length L3 (that is,it is desired that the length L2 is larger than the length L3). Byforming the plug PL1 and the wiring W1 so that the relation of “L2>L3”is established, the connection between the plug PL1 and the wiring W1 inthe direction perpendicular to the semiconductor substrate 1S can beensured as avoiding the increase in the forming amount of the wiring W1so as to be embedded (buried) inside the insulating film SO formed in alower layer than the interlayer insulating film WIL1 (that is, an amountcorresponding to the length L3). Also, by avoiding the increase in theforming amount of the wiring W1 so as to be embedded (buried) inside theinsulating film SO (that is, the amount corresponding to the length L3),the ratio of the portion of the wiring W1 which is formed inside theinsulating film IL2 which is the low dielectric constant film isincreased. In other words, by avoiding the increase in the formingamount of the wiring W1 so as to be embedded (buried) inside theinsulating film SO (that is, the amount corresponding to the length L3),the surface area of the portion of the wiring W1 which is formed insidethe insulating film IL2 which is the low dielectric constant film can beincreased. Therefore, for example, the inter-wiring capacitance betweenthe adjacent wirings W1 can be reduced. Also, by avoiding the formationof the lowermost surface of the wiring W1 at the position close to thegate electrode G1 of the re-channel-type MISFET Q₁, the reduction in thereliability between the wiring W1 and the gate electrode G1 can beavoided. More particularly, by shortening the length L3 as short aspossible, the amount of the portion of the wiring W1 which is formedinside the insulating film SO is decreased, so that the inter-wiringcapacitance can be effectively reduced, and the reduction in thereliability between the wiring W1 and the gate electrode G1 can beavoided. In the first embodiment, by establishing relations of, forexample, “L2=25 nm” and “L3=5 nm”, the above-described condition (therelation of “L2>L3”) is satisfied.

Then (after the formation of the wiring W1), a second-layer wiring isformed by using the dual damascene method as illustrated in FIG. 23.Hereinafter, a method of forming the second-layer wiring will beexplained.

First, as illustrated in FIG. 23, an insulating film IL3 is formed onthe interlayer insulating film WIL1 in which the wiring W1 is formed(buried). The insulating film IL3 is formed of, for example, a siliconnitride film as an insulating film. The insulating film IL3 functions asa barrier insulating film for suppressing diffusion of the copperforming (configuring) the wiring W1. Also, the insulating film IL3 alsoplays a role of an etching stopper in etching (etching for forming acontact hole CNT2 which will be described later) to be performed in alater step. The insulating film IL3 is formed of a silicon nitride filmin the first embodiment, but is not limited to this, and the insulatingfilm IL3 can be formed of, for example, a silicon carbide film, asilicon carbonitride film, or a silicon oxynitride film.

Subsequently, as illustrated in FIG. 23, an insulating film IL4 isformed on the insulating film IL3. The insulating film IL4 is formed of,for example, a SiOC film (a silicon oxide film containing carbon) as alow dielectric constant film, and is formed in order to reduce theinter-wiring capacitance of wirings to be formed later. As theinsulating film IL4, not only the SiOC film but also, for example, aSiOF film, an ULK film, an ELK film, a spin-coated porous MSQ film, or astacked film thereof can be used. An interlayer insulating film WIL2A isformed of a stacked film formed of the insulating film IL3 and theinsulating film IL4.

Sequentially, the contact hole (hole portion, connection hole portion)CNT2 and a wiring trench WT2 are formed in the interlayer insulatingfilm WIL2 by using s photolithography technique and an etchingtechnique. The contact hole CNT2 is formed on a bottom portion of thewiring trench WT2, and the contact hole CNT2 is included in the wiringtrench WT2 in plane when viewed in the plane (when viewed in planeparallel to the main surface of the semiconductor substrate 1S). Theupper surface of the wiring W1 is exposed from the bottom portion of thecontact hole CNT2.

Subsequently, on the interlayer insulating film WIL2 including thecontact hole CNT2 and the inner wall of the wiring trench WT2, forexample, a stacked film formed of a tantalum film and a tantalum nitridefilm is formed as a barrier conductor film WBM2. The barrier conductorfilm WBM2 is formed in order to achieve the adhesiveness with copper tobe formed in a later step and to prevent diffusion of the copper. In thefirst embodiment, the formation of the stacked film formed of thetantalum film and the tantalum nitride film is exemplified as thebarrier conductor film WBM2. However, a single layer of a metal filmsuch as a tantalum film, a single layer of a nitride film (a metalnitride film) such as a titanium nitride film, or a stacked film formedof a metal film and a nitride film (a metal nitride film) such as atitanium nitride film can be also used as the barrier conductor filmWBM2.

Next, on the barrier conductor film WBM2, for example, a copper film isformed as a conductor film CUF2 so as be buried inside the contact holeCNT2 and the wiring trench WT2.

Then, unnecessary portions of the conductor film CUF2 and the barrierconductor film WBM2 formed outside the contact hole CNT2 and the wiringtrench WT2 are removed by polishing by using a CMP method, so that theplug PL2 and the wiring W2 are completed as illustrated in FIG. 23. Thewiring W2 is formed of the conductor film CUF2 and the barrier conductorfilm WBM2 buried and remaining inside the wiring trench WT2, the plugPL2 is formed of the conductor film CUF2 and the barrier conductor filmWBM2 buried and remaining inside the contact hole CNT2, the plug PL2 andthe wiring W2 are integrally formed with each other, and a bottomportion of the plug PL2 is in contact with an upper surface of thewiring W1. Therefore, the wiring W2 is electrically connected to thewiring W1 via the plug PL2 integrally formed with the wiring W2. Thewiring W2 and the plug PL2 are buried in the wiring trench WT1 and thecontact hole CNT2, and are so-called buried wiring (damascene wiring,dual damascene wiring).

As described above, the semiconductor device according to the firstembodiment can be manufactured. Note that multilayered wirings (athird-layer wiring and an upper-layer wiring) may be further formedabove the wiring W2. However, description thereof is omitted here.

In the first embodiment, as described in the step illustrated in FIG.19, the case that the wiring W1 is shifted from the plug PL1 in thedirection parallel to the cross section A has been described in the planview illustrated in FIG. 2. This occurs due to the lithographymisalignment in the etching step for forming the wiring trench WT1illustrated in FIG. 19.

FIG. 24 is a plan view of a principal part of the semiconductor deviceof the first embodiment obtained when the lithography misalignment doesnot occur so that the wiring W1 is formed almost right on the plug PL1,and illustrates a region corresponding to the above-described FIG. 2.Also, FIG. 25 is a cross-sectional view (a cross-sectional view of aprincipal part) taken along a line A2-A2 illustrated in FIG. 24, andcorresponds to the above-described FIG. 3. FIG. 26 is a cross-sectionalview (a cross-sectional view of a principal part) taken along a lineB2-B2 line illustrated in FIG. 24. Hereinafter, a cross section takenalong the line A2-A2 illustrated in FIG. 24 is referred to as a crosssection A2, and a cross section taken along the line B2-B2 illustratedin FIG. 24 is referred to as a cross section B2.

In the first embodiment, a width of a lower surface of the wiring trenchWT1 is formed so as to be almost equal to a diameter of an upper surfaceof the plug PL1 in the cross section A2, and therefore, the lowermostsurface of the wiring W1 illustrated in FIG. 25 is apparently formed atthe same position as that of the upper surface of the plug PL1. That is,in FIG. 25, the lowermost surface of the wiring W1 is apparently formedupper than an upper surface of the interlayer insulating film PIL.However, practically, as similar to the above-described cross section A(corresponding to the above-described FIG. 3), the lowermost surface ofthe wiring W1 is formed inside the insulating film SO also in the caseof FIG. 24. This will be explained with reference to FIG. 26 which is across-sectional view in a direction perpendicular to the cross sectionA2.

As illustrated in FIG. 26, in the cross section B2, the lowermostsurface of the wiring W1 is formed inside the insulating film SO assimilar to the above-described FIG. 21A. As a matter of course, this isthe same in the cross section B in the above-described FIG. 2 (that is,the cross section taken along the line B-B in the above-described FIG.2). That is, both of the cross-sectional view taken along the line B-Bin the above-described FIG. 2 and the cross-sectional view taken alongthe line B2-B2 in FIG. 24 are as illustrated in FIG. 26. Therefore, asillustrated in FIG. 25, even when the lithography misalignment does notoccur so that the wiring W1 is formed almost right on the plug PL1, thelowermost surface of the wiring W1 is formed inside the insulating filmSO as illustrated in FIG. 26, and therefore, effects similar to theabove-described effects are provided.

Also, while the explanation has been made in the first embodiment basedon the case that the diameter of the upper surface of the plug PL1 andthe width of the lower surface of the wiring W1 are almost equal to eachother, their relation is not limited to such a case, and a case that thediameter of the plug PL1 is larger than the width of the lower surfaceof the wiring W1, and a case that the diameter of the plug PL1 issmaller than the width of the lower surface of the wiring W1 can be alsoapplied.

According to the first embodiment, after the polishing for forming theplug PL1 ends, the surface of the insulating film SO is made to recedeso that the upper surface of the plug PL1 is higher than the uppersurface of the insulating film SO, so that the connection between theplug PL1 and the wiring W1 in the direction perpendicular to thesemiconductor substrate 1S can be ensured even if the embedding(burying) amount of the wiring W1 to be formed later inside theinsulating film SO is decreased further than that in the case of themanufacturing step of the above-described comparative example. Further,by forming the wiring W1 so as not to be embedded (buried) inside theinsulating film SO deeper than the manufacturing step of theabove-described comparative example, the surface area of the wiring W1inside the insulating film IL2 which is the low dielectric constant filmis increased. Therefore, even if the microfabrication of the wiringstructure is achieved, the increase in the inter-wiring capacitance canbe avoided.

Second Embodiment

In the first embodiment, the embodiment that the wiring trench WT1 isembedded (buried) inside the insulating film SO so as to form thelowermost surface of the wiring W1 inside the insulating film SO hasbeen explained. As a second embodiment, an embodiment that the wiringtrench WT1 is not embedded (buried) inside the insulating film SO so asto form the wiring W1 inside the interlayer insulating film WIL1 will beexplained.

FIG. 27 is a cross-sectional view of a principal part of a semiconductordevice according to the second embodiment, and illustrates a crosssection corresponding to the cross section A (the cross section takenalong the line A-A) illustrated in the above-described FIG. 2 of thefirst embodiment.

As illustrated in FIG. 27, as similar to the semiconductor device of theabove-described first embodiment, the semiconductor device according tothe second embodiment is formed so that the upper surface of the plugPL1 is higher than the upper surface of the insulating film SO, that is,the upper surface of the interlayer insulating film PIL. Also, assimilar to the semiconductor device of the above-described firstembodiment, the semiconductor device according to the second embodimentis formed so that the lowermost surface of the wiring W1 is lower thanthe upper surface of the plug PL.

That is, the formation of the upper surface of the plug PL1 at theposition higher than the upper surface of the interlayer insulating filmPIL and the formation of the lower surface of the wiring W1 (morespecifically, the lowermost surface of the wiring W1) at the positionlower than the upper surface of the plug PL1 are common among theabove-described first embodiment, the present second embodiment, and thethird to seventh embodiments described later. Therefore, when the wiringtrench WT1 is formed, the formation of the lower surface of the wiringtrench WT1 (more specifically, the lowermost surface of the wiringtrench WT1) at the position lower than the upper surface of the plug PL1is common among the above-described first embodiment, the present secondembodiment, and the third to seventh embodiments described later.

On the other hand, in the semiconductor device according to the secondembodiment, the wiring W1 is not formed inside the insulating film SOand the whole wiring W1 is formed inside the interlayer insulating filmWIL1 as different from the above-described first embodiment. That is,the lowermost surface of the wiring W1 is formed inside the interlayerinsulating film WIL1.

In the second embodiment, the plug PL1 is formed so as to protrude fromthe upper surface of the insulating film SO, that is, the upper surfaceof the interlayer insulating film PIL, so that the connection betweenthe plug PL1 and the wiring W1 can be ensured even if the whole wiringW1 is formed inside the interlayer insulating film WIL1. Also, in thesecond embodiment, a ratio of a portion of the wiring W1 which is formedinside the insulating film IL2 which is the low dielectric constant filmis larger than that in the above-described first embodiment, so that thesurface area of the wiring W1 which is formed in the insulating film IL2which is the low dielectric constant film is increased, and therefore,the effect of reducing the inter-wiring capacitance can be expected morethan the above-described first embodiment.

Hereinafter, a method of manufacturing the semiconductor deviceaccording to the second embodiment will be explained with reference tothe drawings. Each of FIGS. 28 to 33 is a cross-sectional view of aprincipal part of the semiconductor device according to the secondembodiment in a manufacturing step, and illustrates a cross sectioncorresponding to the above-described cross section A.

The steps illustrated in the above-described FIGS. 4 to 8 of theabove-described first embodiment are also similarly performed in thesecond embodiment.

Note that, also in the second embodiment, in the following steps, anupper surface of the insulating film SO is synonymously used with anupper surface of the interlayer insulating film PIL, and an inside ofthe insulating film SO is synonymously used with an inside of theinterlayer insulating film PIL.

After the step illustrated in the above-described FIG. 8 of theabove-described first embodiment, the upper surface of the insulatingfilm SO is made to recede in the second embodiment as illustrated inFIG. 28. In the second embodiment, this receding amount (an amount ofmaking the upper surface of the insulating film SO to recede) is largerthan the receding amount (the amount of making the upper surface of theinsulating film SO to recede) in the above-described first embodiment,and is, for example, 35 nm. As described in the first embodiment above,the method of making the insulating film SO to recede can be performedby dry etching, wet etching, or a CMP method by using a polishing liquidhaving a high selectivity for the insulating film SO.

After the insulating film SO is made to recede, the upper surface of theinsulating film SO is lower than the upper surface of the plug PL1 asillustrated in FIG. 28. That is, the upper surface of the insulatingfilm SO is made to recede so that the plug PL1 protrudes from the uppersurface of the insulating film SO. In the second embodiment, thereceding amount of the insulating film SO is large as described above,and therefore, the protruding amount of the plug PL1 from the uppersurface of the insulating film SO, that is, a distance between the uppersurface of the insulating film SO and the upper surface of the plug PL1is larger than that of the above-described first embodiment. Asdescribed above, when the receding amount of the insulating film SO is,for example, 35 nm, the protruding amount of the plug PL1 from the uppersurface of the insulating film SO, that is, the distance between theupper surface of the insulating film SO and the upper surface of theplug PL1 is 35 nm.

Next, as similar to the above-described first embodiment, a first-layerwiring is formed by a single damascene method. Hereinafter, a method offorming the first-layer wiring will be explained.

First, as illustrated in FIG. 29, the insulating film IL1 is formed onthe interlayer insulating film PIL (the insulating film SO) and on theplug PL1, and then, the insulating film IL2 is formed on the insulatingfilm IL1. The insulating film IL1 is formed thinner than the insulatingfilm IL2. A thickness of the insulating film IL1 is, for example, 15 nm,and a thickness of the insulating film IL2 is, for example, nm. By theseinsulating film IL1 and insulating film IL2, the interlayer insulatingfilm WIL1 of the first-layer wiring is formed. Also in the secondembodiment, as similar to the above-described first embodiment, theinsulating film IL2 is formed of, for example, a SiOC film as a lowdielectric constant film in order to reduce the inter-wiringcapacitance. Further, as similar to the above-described firstembodiment, the insulating film IL1 is formed of, for example, a siliconoxide film as an insulating film for covering the exposed semiconductorsubstrate 1S in order to prevent the abnormal electrical discharge uponthe formation of the SiOC film of the insulating film.

Next, as illustrated in FIGS. 30A and 30B, the wiring trench WT1 isformed in the interlayer insulating film WIL1. A depth of the interlayerinsulating film WIL1 is, for example, 90 nm.

In the second embodiment, the wiring trench WT1 is formed inside theinterlayer insulating film WIL1, and the lowermost surface of the wiringtrench WT1 is also formed inside the interlayer insulating film WIL1.That is, in the second embodiment, the wiring trench WT1 is not embedded(buried) inside the insulating film SO, and therefore, the lowermostsurface of the wiring trench WT1 is formed inside the interlayerinsulating film WIL1.

Each of FIGS. 30A and 30B illustrates a case that the wiring trench WT1is formed at a position shifted from the plug PL1 in a directionparallel to the cross section A as similar to the above-described FIG.19 according to the above-described first embodiment.

FIG. 30A illustrates a case that the whole of the lowermost surface ofthe wiring trench WT1 is formed inside the insulating film IL1. In thiscase, the lowermost surface of the wiring trench WT1 is formed of anexposed surface of the insulating film IL1, and the lowermost surface ofthe wiring W1 to be buried in this wiring trench WT1 later is in contactwith this exposed surface of the insulating film IL1. Note that, also inthe second embodiment, a state that the wiring trench WT1 is formedinside the interlayer insulating film WIL1 also includes a state thatthe lowermost surface of the wiring trench WT1 matches with the lowersurface of the insulating film IL1 (that is, the lowermost surface ofthe wiring trench WT1 is on the same plane as that of the lower surfaceof the insulating film IL1). In this case, the lowermost surface of thewiring trench WT1 is formed of the upper surface of the insulating filmSO, and the lowermost surface of the wiring W1 to be buried in thiswiring trench WT1 later is in contact with the upper surface of theinsulating film SO.

When the wiring trench WT1 is formed as illustrated in FIG. 30A, thewiring trench WT1 can be formed so that the lowermost surface of thewiring trench WT1 is positioned lower than the upper surface of the plugPL1 and also higher than (for example, 5 nm higher than) the uppersurface of the insulating film SO (the interlayer insulating film PIL).

On the other hand, as illustrated in FIG. 30B, a case that the lowermostsurface of the wiring trench WT1 is formed over both of the insulatingfilm IL1 and the insulating film IL2, that is, a case that the lowermostsurface of the wiring trench WT1 is formed inside the insulating filmIL1 and in the insulating film IL2 is also included in the secondembodiment. In this case, the lowermost surface of the wiring trench WT1is formed of the exposed surfaces of the insulating films IL1 and IL2,and the lowermost surface of the wiring W1 to be buried in this wiringtrench WT1 later is in contact with these exposed surfaces of theinsulating films IL1 and IL2.

In the step illustrated in the above-described FIG. 28, when thereceding amount of the insulating film SO is further increased so as tobe, for example, 50 nm, and besides, a thickness of the insulating filmIL2 is, for example, 95 nm, the wiring trench WT1 is formed so that thedepth of the wiring trench WT1 is equal to the depth of the wiringtrench WT1 of FIG. 30A and that the lowermost surface of the wiringtrench WT1 is over both of the insulating film IL1 and the insulatingfilm IL2 as illustrated in FIG. 30B. When the wiring trench WT1 isformed as illustrated in FIG. 30B of the second embodiment, the wiringtrench WT1 can be formed so that the lowermost surface of the wiringtrench WT1 is positioned lower than the upper surface of the plug PL1,and besides, for example, 20 nm higher than the upper surface of theinsulating film SO (the interlayer insulating film PIL).

In order to form the wiring trench WT1 in the state as illustrated inFIG. 30A, as described in the first embodiment above, the interlayerinsulating film WIL1 may be dry-etched by using a photoresist pattern (apatterned photoresist film) formed by a photolithography technique as amask (an etching mask). In this etching step, an etching endpoint of theinsulating film IL2 is detected in, for example, a scribe region at thetime when the etching of the insulating film IL2 reaches a surface ofthe insulating film IL1 (that is, at the time when a part of the surfaceof the insulating film IL1 is exposed). Also after that (after theendpoint detection), as similar to the first embodiment, the etching(the etching of the insulating film IL1) in which etching time iscontrolled to a predetermined time (a certain time) is performed, sothat the wiring trench WT1 is completed. Finally, at least a part of theupper surface (the upper portion) of the plug PL1 and a part of the sidesurfaces thereof are exposed because of the wiring trench WT1. In thiscase, the step of forming the wiring trench WT1 includes: a first stepof etching the insulating film IL2; a second step of detecting theetching endpoint of the insulating film IL2 when the etching in thefirst step reaches the upper surface of the insulating film IL1; and athird step of etching the insulating film IL1 after the second step. Inthis manner, by detecting the etching endpoint of the insulating filmIL2, a process of the dry etching for forming the whole wiring trenchWT1 is divided into two stages (the first step and the third step), sothat the processing accuracy of the etching can be improved.

On the other hand, in order to form the wiring trench WT1 in the stateas illustrated in FIG. 30B, it is required to perform the whole etchingfor forming the wiring trench WT1 by a step of etching (etching of theinsulating film IL2 and the insulating film IL1) in which etching timeis controlled. This is because, in the step of forming the wiring trenchWT1 as illustrated in FIG. 30B, the etching thereof does not reach theinsulating film IL1 in the region where the endpoint detection isobserved such as the scribe region. Therefore, the processing accuracyof the etching for forming the wiring trench WT1 can be improved in thecase illustrated in FIG. 30A better than the case illustrated in FIG.30B.

Also, when the insulating film IL1 remains on the side surfaces of theplug PL1 even after the dry etching in this step (that is, after the dryetching step for forming the wiring trench WT1), it is preferred toremove the insulating film IL1 remaining on the side surfaces of theplug PL1 so as to expose the side surfaces of the plug PL1 from thewiring trench WT1 by further performing wet etching or others. In thismanner, an exact connection between the wiring W1 to be formed in alater step and the plug PL1 can be ensured.

Also in the second embodiment, since the insulating film SO is made torecede by the step illustrated in FIG. 28, the upper surface of the plugPL1 is formed at a position higher than the upper surface of theinsulating film SO. On the other hand, the lowermost surface of thewiring trench WT1 is formed inside the interlayer insulating film WIL1,and besides, the lowermost surface of the wiring trench WT1 is formed ata position lower than the upper surface of the plug PL1. Therefore, atleast a part of the upper surface of the plug PL1 and a part of the sidesurfaces of the plug PL1 are exposed because of the wiring trench WT1,and therefore, when a conductive film is buried in the wiring trench WT1in a later step, the conductive film buried in this wiring trench WT1and the plug PL1 can be reliably connected to each other.

Further, in the second embodiment, the etching (etching for forming thewiring trench WT1) is performed so that the whole wiring trench WT1 isformed inside the interlayer insulating film WIL1 but is not formedinside the insulating film SO, and therefore, the lowermost surface ofthe wiring trench WT1 is formed at a position separated from the gateelectrode G1 by at least a distance from the upper surface of the gateelectrode G1 to the upper surface of the insulating film SO.

Next, as similar to the above-described first embodiment, the barrierconductor film WBM is formed on the interlayer insulating film WIL1including a portion on the inner wall (the side walls and the bottomportion) of the wiring trench WT1, the conductor film CUF is formed onthe barrier conductor film WBM so as to be buried inside the wiringtrench WT1, and then, unnecessary portions of the conductor film CUF andthe barrier conductor film WBM formed outside the wiring trench WT1 arepolished and removed by using a CMP method, so that the wiring W1 isformed as illustrated in FIG. 31. The wiring W1 is formed of theconductor film CUF and the barrier conductor film WBM buried andremaining inside the wiring trench WT1. The wiring trench WT1 is formedinside the interlayer insulating film WIL1, and the lowermost surface ofthe wiring trench WT1 is also formed inside the interlayer insulatingfilm WIL1, and therefore, the lowermost surface of the wiring W1 formedby burying the barrier conductor film WBM and the conductor film CUF inthe wiring trench WT1 is also formed inside the interlayer insulatingfilm WIL1.

FIG. 31 illustrates the case that the lowermost surface of the wiring W1is formed over both of the insulating film IL1 and the insulating filmIL2, that is, the case that the wiring W1 is formed by burying thebarrier conductor film WBM and the conductor film CUF in the wiringtrench WT1 formed as illustrated in FIG. 30B. On the other hand, theabove-described FIG. 27 illustrates the case that the wiring W1 isformed by burying the barrier conductor film WBM and the conductor filmCUF in the wiring trench WT1 formed as illustrated in FIG. 30A. In FIGS.27 and 31, the depth of the wiring W1 is similar to that of the wiringtrench WT1, which is, for example, 90 nm, and the position of thelowermost surface of the wiring W1 is also similar to the position ofthe lowermost surface of the wiring trench WT1 illustrated in FIGS. 30Aand 30B. That is, the whole of the lowermost surface of the wiring W1 isformed inside the insulating film IL1 in the case of FIG. 27, but thelowermost surface of the wiring W1 is formed inside the insulating filmIL1 and the insulating film IL2 in the case of FIG. 31.

Also in the second embodiment, as illustrated in FIGS. 27 and 31, theupper surface of the plug PL1 is formed at a position higher than theupper surface of the insulating film SO, and besides, the lowermostsurface of the wiring W1 is formed at a position lower than the uppersurface of the plug PL1, and therefore, at least a part of the uppersurface of the plug PL1 and a part of the side surfaces thereof arecovered with the wiring W1. In this manner, the connection between theplug PL1 and the wiring W1 can be ensured, so that the reliability ofthe connection between the plug PL1 and the wiring W1 can be improved.

Further, in the second embodiment, the receding amount of the insulatingfilm SO from the upper surface of the plug PL1 is larger than that ofthe first embodiment as described above. Therefore, even when the plugPL1 and the wiring W1 are formed so that the connection between the plugPL1 and the wiring W1 is sufficiently ensured, the wiring W1 is notformed inside the insulating film SO but the whole wiring W1 is formedinside the interlayer insulating film WIL1. That is, even when the plugPL1 and the wiring W1 are formed so that the connection between the plugPL1 and the wiring W1 is sufficiently ensured, the lowermost surface ofthe wiring W1 is not formed inside the insulating film SO but the wholewiring W1 is formed inside the interlayer insulating film WIL1. In thismanner, as ensuring the connection between the plug PL1 and the wiringW1, the ratio of the portion of the wiring W1 which is formed inside theinsulating film IL2 which is the low dielectric constant film can beincreased. In other words, as ensuring the connection between the plugPL1 and the wiring W1, the surface area of the wiring W1 which is formedinside the insulating film IL2 which is the low dielectric constant filmcan be increased. Therefore, for example, the inter-wiring capacitancebetween adjacent wirings W1 can be reduced.

In the second embodiment, since the whole wiring W1 is formed inside theinterlayer insulating film WIL1, the ratio of the portion of the wiringW1 which is formed inside the low dielectric constant film (theinsulating film IL2) can be increased more than that of theabove-described first embodiment. Therefore, the inter-wiringcapacitance can be reduced further than that of the above-describedfirst embodiment.

Still further, the ratio of the portion of the wiring W1 which is formedinside the insulating film IL2 which is the low dielectric constant filmis larger in the case that the wiring trench WT1 and the wiring W1buried therein are formed as illustrated in FIG. 31 than the case thatthe wiring trench WT1 and the wiring W1 buried therein are formed asillustrated in FIG. 27, and therefore, it can be said that the effect ofreducing the inter-wiring capacitance is large.

Still further, in the second embodiment, by forming the upper surface ofthe plug PL1 higher than the upper surface of the insulating film SO,even if the whole wiring W1 is formed inside the interlayer insulatingfilm WIL1, the length L1 by which the wiring W1 and the plug PL1 areoverlapped with each other in the direction perpendicular to thesemiconductor substrate 1S can be ensured by, for example, 30 nm. Thatis, without the state that the wiring W1 is embedded (buried) inside theinsulating film SO, the length L1 by which the wiring W1 and the plugPL1 are overlapped with each other in the direction perpendicular to thesemiconductor substrate 1S is ensured. Therefore, even if themicrofabrication of wirings is achieved, the state that the wiring W101is formed inside the insulating film SO as the case of the manufacturingstep of the above-described comparative example is not provided, andtherefore, it is possible to avoid the increase in the inter-wiringcapacitance between the wirings W1 due to the increase in the ratio ofthe portion of the wiring W1 which is formed inside the insulating filmSO.

Still further, as described above, by forming the lowermost surface ofthe wiring trench WT1 so as to be separated from the gate electrode G1by a predetermined distance (a certain distance) or farther, theshortening of the distance between the wiring W1 and the gate electrodeG1 can be avoided, so that the reduction in the reliability between thewiring W1 and the gate electrode G1 can be avoided. In the secondembodiment, the case that the insulating film IL2 is formed of the lowdielectric constant film has been described. However, it is not alwaysrequired to form the insulating film IL2 from the low dielectricconstant film regarding the effect of avoidance of the reduction in thereliability between the wiring W1 and the gate electrode G1. In thiscase, the insulating film IL2 can be formed of, for example, a siliconoxide film as an insulating film.

In the second embodiment, the above-described effect can be obtained byforming the upper surface of the plug PL1 so as to be even slightlyhigher than the upper surface of the insulating film SO as similar tothe above-described first embodiment. Here, a more preferable conditionused when the plug PL1 and the wiring W1 are formed will be explained.

FIG. 32 is an enlarged cross-sectional view of a principal part (apartially-enlarged cross-sectional view) of an enlarged periphery of aregion where the plug PL1 and the wiring W1 are connected to each otherin FIG. 27. Hereinafter, with reference to FIG. 32, a more preferablecondition for the formation of the plug PL1 and the wiring W1 will beexplained.

As illustrated in FIG. 32, a difference between a distance from theupper surface of the insulating film SO to the upper surface of the plugPL1 and a thickness of the insulating film IL1 is set as a length L4.Meanwhile, a difference between the thickness of the insulating film IL1and a distance from the upper surface of the insulating film SO to thelowermost surface of the wiring W1 is set as a length L5. Here, in thecase of FIG. 32, addition of the length L4 and the length L5 correspondsto the above-described length L1 (that is, “L1=L4+L5”). Note that, foreasily understanding, in FIG. 32, the upper surface of the insulatingfilm SO is provided with a reference symbol SOSF so as to be representedas an upper surface SOSF of the insulating film SO, the upper surface ofthe plug PL1 is provided with a reference symbol PLSF so as to berepresented as an upper surface PLSF of the plug PL1, the lowermostsurface of the wiring W1 is provided with a reference symbol W1SF so asto be represented as the lowermost surface W1SF of the wiring W1, andthe thickness of the insulating film IL1 is provided with a referencesymbol L21 so as to be represented as a thickness L21 of the insulatingfilm IL1.

At this time, it is desired to establish a relation of “L4>L5” betweenthe length L4 and the length L5 (that is, it is desired that the lengthL4 is larger than the length L5). By forming the plug PL1 and the wiringW1 so as to establish the relation of “L4>L5”, the connection betweenthe plug PL1 and the wiring W1 in the direction perpendicular to thesemiconductor substrate 1S can be ensured as avoiding increase in aforming amount of the wiring W1 (that is, an amount corresponding to thelength L5) which is embedded (buried) inside the insulating film IL1which is a part of the interlayer insulating film WIL1 and is formed ona lower side of the low dielectric constant film (the insulating filmIL2). Also, by avoiding the increase in the forming amount of the wiringW1 (that is, the amount corresponding to the length L5) which isembedded (buried) inside the insulating film IL1, the ratio of theportion of the wiring W1 which is formed inside the insulating film IL2which is the low dielectric constant film is increased. In other words,by avoiding the increase in the forming amount of the wiring W1 (thatis, the amount corresponding to the length L5) which is embedded(buried) inside the insulating film IL1, the area where the wiring W1and the insulating film IL2 which is the low dielectric constant filmare in contact with each other can be increased. Therefore, for example,the inter-wiring capacitance between adjacent wirings W1 can be reduced.More particularly, by shortening the length L5 as small as possible, theamount of the portion of the wiring W1 which is formed inside theinsulating film IL1 is decreased, so that the inter-wiring capacitancecan be effectively reduced. In the second embodiment, by settingrelations of, for example, “L4=20 nm” and “L5=10 nm”, theabove-described condition (the relation of “L4>L5”) is satisfied.

FIG. 33 is an enlarged cross-sectional view of a principal part (apartially-enlarged cross-sectional view) an enlarged periphery of aregion where the plug PL1 and the wiring W1 are connected to each otherin FIG. 31. Hereinafter, with reference to FIG. 33, a more preferablecondition for the formation of the plug PL1 and the wiring W1 will beexplained.

As illustrated in FIG. 33, a distance from the lowermost surface of thewiring W1 to the upper surface of the plug PL1 is set as a length L6.Meanwhile, a difference between a thickness of the insulating film IL1and a distance from the upper surface of the insulating film SO to thelowermost surface of the wiring W1 is set as a length L7. Here, in thecase of FIG. 33, the length L6 corresponds to the above-described lengthL1 (that is, “L6=L1”). Note that, for easily understanding, in FIG. 33,the upper surface of the insulating film SO is provided with a referencesymbol SOSF so as to be represented as an upper surface SOSF of theinsulating film SO, the upper surface of the plug PL1 is provided with areference symbol PLSF so as to be represented as an upper surface PLSFof the plug PL1, the lowermost surface of the wiring W1 is provided witha reference symbol W1SF so as to be represented as the lowermost surfaceW1SF of the wiring W1, and the thickness of the insulating film IL1 isprovided with a reference symbol L21 so as to be represented as athickness L21 of the insulating film IL1.

At this time, it is desired to establish a relation of “L6>L7” betweenthe length L6 and the length L7 (that is, it is desired that the lengthL6 is larger than the length L7). By forming the plug PL1 and the wiringW1 so as to establish the relation of “L6>L7”, the wiring W1 can beformed inside the interlayer insulating film WIL1 as decreasing areceding amount of the insulating film SO in the step of making theinsulating film SO to recede as illustrated in the above-described FIG.28, and besides, as ensuring the connection between the plug PLI1 andthe wiring W1 in the direction perpendicular to the semiconductorsubstrate 1S in a later step. Therefore, reduction in controllability ofthe step of making the insulating film SO to recede and repeatabilitythereof can be suppressed or prevented.

Also, the ratio of the portion of the wiring W1 which is formed insidethe insulating film IL2 which is the low dielectric constant film islarger in the case that the wiring W1 is formed as illustrated in FIG.33 than the case that the wiring W1 is formed as illustrated in FIG. 32,and therefore, the effect of reducing the inter-wiring capacitance islarge. More particularly, by shortening the length L7 as small aspossible, the receding amount of the insulating film SO in the stepillustrated in FIG. 28 can be minimized, and therefore, this is morepreferable. In the second embodiment, by setting relation of, forexample, “L6=30 nm” and “L7=5 nm”, the above-described condition (therelation of “L6>L7”) is satisfied.

In a later step (a step after the formation of the wiring W1), assimilar to that of the above-described first embodiment, a second-layerwiring is formed. However, illustration and explanation thereof areomitted here.

Also in the second embodiment, the manufacturing method has beenexplained as similar to the above-described first embodiment withreference to the drawings in the case that the diameter of the uppersurface of the plug PL1 and the width of the lower surface of the wiringW1 are formed so as to be about equal to each other. However, themanufacturing step is not limited to such a case, and can be effectivelyapplied to a case that the diameter of the plug PL1 is larger than thewidth of the lower surface of the wiring W1 and a case that the diameterof the plug PL1 is smaller than the width of the lower surface of thewiring W1.

According to the second embodiment, after the polishing for forming theplug PL1, the surface (the upper surface) of the insulating film SO ismade to recede so that the upper surface of the plug PL1 is higher thanthe upper surface of the insulating film SO. By making the surface (theupper surface) of the insulating film SO to recede, the connectionbetween the plug PL1 and the wiring W1 in the direction perpendicular tothe semiconductor substrate 1S can be ensured even if the wiring W1 tobe formed later is not formed so as to be embedded (buried) inside theinsulating film SO. Further, by forming the wiring W1 so as not to beembedded (buried) inside the insulating film SO, that is, by forming thewiring W1 only inside the interlayer insulating film WIL1, the ratio ofthe portion of the wiring W1 which is formed inside the insulating filmIL2 which is the low dielectric constant film is increased, and thesurface area of the wiring W1 which is formed inside the insulating filmIL2 which is the low dielectric constant film is increased, andtherefore, the inter-wiring capacitance can be reduced. Still further,by forming the wiring W1 so as not to be embedded (buried) inside theinsulating film SO, the increase in the inter-wiring capacitance can beavoided even if the microfabrication of wirings is achieved.

Third Embodiment

In the above-described first and second embodiments, the interlayerinsulating film WIL1 in which the wiring W1 is formed is formed of thestacked film formed of the insulating film IL1 and the insulating filmIL2. However, in a third embodiment, the interlayer insulating film WIL1is formed of one layer of the insulating film IL2 without forming theinsulating film IL1 as a part of the interlayer insulating film WIL.

FIG. 34 is a cross-sectional view of a principal part of a semiconductordevice according to the third embodiment, and illustrates a crosssection corresponding to the cross section A (the cross section takenalong the line A-A) illustrated in the above-described FIG. 2 of theabove-described first embodiment.

As illustrated in FIG. 34, in the semiconductor device according to thethird embodiment, the upper surface of the plug PL1 is formed higherthan the upper surface of the insulating film SO, that is, the uppersurface of the interlayer insulating film PIL as similar to thesemiconductor devices of the above-described first and secondembodiments. Also, in the semiconductor device according to the thirdembodiment, the whole wiring W1 is formed inside the interlayerinsulating film WIL1 as similar to the above-described secondembodiment. That is, the lowermost surface of the wiring W1 is formedinside the interlayer insulating film WIL1. On the other hand, in thesemiconductor device according to the third embodiment, the insulatingfilm IL1 is not formed as different from the above-described first andsecond embodiments. That is, the interlayer insulating film WIL1 isformed of one layer of the insulating film IL2. Therefore, in thesemiconductor device according to the third embodiment, the whole wiringW1 is formed inside the insulating film IL2 which is the low dielectricconstant film.

In the third embodiment, by forming the plug PL1 so as to protrude fromthe upper surface of the insulating film SO, that is, the upper surfaceof the interlayer insulating film PIL, the connection between the plugPL1 and the wiring W1 can be ensured even if the whole wiring W1 isformed inside the insulating film IL2. Also, in the third embodiment,since the whole wiring W1 is formed inside the insulating film IL2 whichis the low dielectric constant film, the effect of reducing theinter-wiring capacitance can be expected further than theabove-described first and second embodiments.

Hereinafter, a method of manufacturing the semiconductor deviceaccording to the third embodiment will be explained with reference tothe drawings. Each of FIGS. 35 to 37 is a cross-sectional view of aprincipal part of the semiconductor device of the third embodiment in amanufacturing step, and illustrates a cross section corresponding to theabove-described cross section A.

The steps illustrated in the above-described FIGS. 4 to 8 of theabove-described first embodiment also similarly performed in the thirdembodiment.

Note that, also in the third embodiment, in the following steps, anupper surface of the insulating film SO is synonymously used with anupper surface of the interlayer insulating film PIL, and an inside ofthe insulating film SO is synonymously used with an inside of theinterlayer insulating film PIL.

After the step illustrated in the above-described FIG. 8 of theabove-described first embodiment, the upper surface of the insulatingfilm SO is made to recede in the third embodiment as illustrated in FIG.35. A receding amount of the upper surface of the insulating film SO is,for example, 35 nm. As described in the above-described firstembodiment, the method of making the insulating film SO to recede can beperformed by dry etching, wet etching, or a CMP method by using apolishing liquid having a high selectivity for the insulating film SO.After the insulating film SO is made to recede, the upper surface of theinsulating film SO is lower than the upper surface of the plug PL1 asillustrated in FIG. 35. That is, the upper surface (the surface) of theinsulating film SO is made to recede so that the plug PL1 protrudes fromthe upper surface of the insulating film SO. As described above, sincethe receding amount of the insulating film SO is, for example, 35 nm, aprotruding amount of the plug PL1 from the insulating film SO, that is,a distance between the upper surface of the insulating film SO and theupper surface of the plug PL1 is, for example, 35 nm.

Next, a first-layer wiring is formed by a single damascene method.Hereinafter, a method of forming the first-layer wiring will beexplained.

First, as illustrated in FIG. 36, the insulating film IL2 is formed onthe interlayer insulating film PIL (the insulating film SO) and on theplug PL1. The insulating film IL2 is formed on the interlayer insulatingfilm PIL (the insulating film SO) so as to cover a portion of the plugPL1 protruding from the upper surface of the interlayer insulating filmPIL (the insulating film SO). The insulating film IL2 is formed of, forexample, a SiOC film as a low dielectric constant film in order toreduce the inter-wiring capacitance. A thickness of the insulating filmIL2 is, for example, 95 nm. In the third embodiment, as different fromthe above-described first and second embodiments, the insulating filmIL1 is not formed before the formation of the insulating film IL2.

In the above-described first and second embodiments, the insulating filmIL2 is formed in order to prevent abnormal electrical discharge upon theformation of the SiOC film. However, when there is no risk of theabnormal electrical discharge upon the formation of the SiOC film, whenthere is no requirement to form the insulating film IL2 by a lowdielectric constant film other than the SiOC film or others so as toprevent the abnormal electrical discharge, or when there is norequirement to form the insulating film IL1 even as the etching stopper,the insulating film IL2 can be formed on the interlayer insulating filmPIL (insulating film SO) including the portion on the plug PL1 withoutforming the insulating film IL1, and this manner corresponds to thethird embodiment. Therefore, in the third embodiment, the interlayerinsulating film WIL1 is formed of one layer of the insulating film IL2,and the insulating film IL2 indicates the interlayer insulating filmWIL1 in the following steps.

Next, as illustrated in FIG. 37, the wiring trench WT1 is formed in theinsulating film IL2. With the wiring trench WT1, at least a part of theupper surface (the upper portion) of the plug PL1 and a part of the sidesurfaces thereof are exposed. A depth of the wiring trench WT1 is, forexample, 90 nm.

In the third embodiment, the whole wiring trench WT1 is formed insidethe insulating film IL2. That is, in the third embodiment, the wiringtrench WT1 is not embedded inside the insulating film SO, and thelowermost surface of the wiring trench WT1 is formed inside theinsulating film IL2 which is the low dielectric constant film.Therefore, the lowermost surface of the wiring trench WT1 is formed ofthe exposed surface of the insulating film IL2, and the lowermostsurface of the wiring W1 to be buried in this wiring trench WT1 later isin contact with this exposed surface of the insulating film IL2. Thelowermost surface of the wiring trench WT1 is positioned lower than theupper surface of the plug PL1, and is positioned, for example, 5 nmhigher than the upper surface of the insulating film SO. FIG. 37illustrates a case that the wiring trench WT1 is formed at a positionshifted from the plug PL1 in a direction parallel to the cross section Aas similar to the above-described FIG. 19 in the above-described firstembodiment.

In order to form the wiring trench WT1, the insulating film IL2 isdry-etched by using a photoresist pattern (a patterned photoresist film)formed by a photolithography technique as a mask (an etching mask) asdescribed in the first embodiment. If the insulating film IL2 remains ona side surface of the plug PL1 after this dry etching, it is preferredto further perform wet etching or others after this dry etching so as toremove the insulating film IL2 remaining on the side surface of the plugPL1 and expose the side surface of the plug PL1 from the wiring trenchWT1. In this manner, the exact connection between the wiring W1 to beformed in a later step and the plug PL1 can be ensured.

Also in the third embodiment, since the insulating film SO is made torecede by the step illustrated in FIG. 35, the upper surface of the plugPL1 is formed at a position higher than the upper surface of theinsulating film SO. On the other hand, the lowermost surface of thewiring trench WT1 is formed inside the insulating film IL2, and besides,the lowermost surface of the wiring trench WT1 is formed at a positionlower than the upper surface of the plug PL1. Therefore, at least a partof the upper surface of the plug PL1 and a part of the side surfaces ofthe plug PL1 are exposed because of the wiring trench WT1, so that, whena conductive film is buried in the wiring trench WT1 in a later step,the conductive film buried in this wiring trench WT1 and the plug PL1can be reliably connected to each other.

In order to form the wiring trench WT1, the interlayer insulating filmWIL1 may be dry-etched by using a photoresist pattern (a patternedphotoresist film) formed by a photolithography technique as a mask (anetching mask) as described in the above-described first embodiment.However, in the third embodiment, the interlayer insulating film WIL1 isformed of one layer of the insulating film IL2, and besides, the lowersurface of the wiring trench WT1 is formed inside the insulating filmIL2, and therefore, there is no film for detecting an endpoint of thedry etching. Therefore, in the third embodiment, the etching for formingthe wiring trench WT1 is performed by controlling etching time for theinsulating film IL2. By performing the etching (the etching for theinsulating film IL2) with controlling the etching time as the etchingfor forming the wiring trench WT1, the wiring trench WT1 having adesired depth can be formed even when the film for detecting theendpoint or an etching-stopper film is not formed. However, in the thirdembodiment, it is required to etch the whole wiring trench WT1 bycontrolling the etching time, and therefore, the detection of theendpoint as in the above-described first and second embodiments is moreadvantageous in a viewpoint of improvement of the processing accuracy ofthe wiring trench WT1.

Further, in the third embodiment, the etching for forming the wiringtrench WT1 is performed so that the whole wiring trench WT1 is formedinside the insulating film IL2 but the wiring trench WT1 is not formedinside the insulating film SO, and therefore, the lowermost surface ofthe wiring trench WT1 is formed at a position separated from the gateelectrode G1 by at least a distance from the upper surface of the gateelectrode G1 to the upper surface of the insulating film SO.

Next, as similar to the above-described first embodiment, the wiring W1is formed as illustrated in the above-described FIG. 34 by forming thebarrier conductor film WBM on the insulating film IL2 including theportion on the inner wall (the side surfaces and the bottom portion) ofthe wiring trench WT1, forming the conductor film CUF on the barrierconductor film WBM so as to be buried (be filled) inside the wiringtrench WT1, and then, polishing and removing unnecessary portions of theconductor film CUF and the barrier conductor film WBM formed outside thewiring trench WT1 by using a CMP method. The wiring W1 is formed of theconductor film CUF and the barrier conductor film WBM buried andremaining inside the wiring trench WT1. A depth of the wiring W1 issimilar to a depth of the wiring trench WT1, which is, for example, 90nm. Also, a position of the lowermost surface of the wiring W1 issimilar to a position of the lowermost surface of the wiring trench WT1formed in FIG. 37. The wiring trench WT1 is formed inside the insulatingfilm IL2, and the lowermost surface of the wiring trench WT1 is alsoformed inside the insulating film IL2, and therefore, the lowermostsurface of the wiring W1 formed by burying the barrier conductor filmWBM and the conductor film CUF in the wiring trench WT1 is also formedinside the insulating film IL2. Further, the upper surface of the plugPL1 is formed at a position higher than the upper surface of theinsulating film SO, and besides, the lowermost surface of the wiring W1is formed at a position lower than the upper surface of the plug PL1,and therefore, at least each of a part of the upper surface of the plugPL1 and a part of the side surfaces thereof are covered with the wiringW1. In this manner, the connection between the plug PL1 and the wiringW1 can be ensured, so that the reliability of the connection between theplug PL1 and the wiring W1 can be improved.

Still further, in the third embodiment, the interlayer insulating filmWIL1 in which the wiring W1 is formed is formed of one layer of theinsulating film IL2 as different from the above-described first andsecond embodiments, and therefore, the whole wiring W1 is formed insidethe low dielectric constant film (the insulating film IL2). Therefore,the inter-wiring capacitance can be further reduced than those of theabove-described first and second embodiments in which the wiring W1 canbe also formed in a portion other than the inside of the low dielectricconstant film.

Still further, in the third embodiment, by forming the upper surface ofthe plug PL1 so as to be higher than the upper surface of the insulatingfilm SO, the length L1 by which the wiring W1 and the plug PL1 areoverlapped with each other in the direction perpendicular to thesemiconductor substrate 1S is ensured as, for example, 30 nm even whenthe whole wiring W1 is formed inside the insulating film IL2. That is,the length L1 by which the wiring W1 and the plug PL1 are overlappedwith each other in the direction perpendicular to the semiconductorsubstrate 1S is ensured even if the wiring W1 is formed so as not to beembedded inside the insulating film SO. Therefore, even if themicrofabrication of the wiring structure is achieved, the state that thewiring W101 is formed inside the insulating film SO as the case of themanufacturing step of the above-described comparative example is notprovided, and therefore, the increase in the inter-wiring capacitancebetween the wirings W1 due to the formation of the wiring W1 inside theinsulating film SO can be avoided.

Still further, as described above, by forming the lowermost surface ofthe wiring trench WT1 so as to be separated from the gate electrode G1by a predetermined distance (a certain distance) or farther, theshortening of the distance between the wiring W1 and the gate electrodeG1 can be avoided, and therefore, the reduction in the reliabilitybetween the wiring W1 and the gate electrode G1 can be avoided. In thethird embodiment, the case that the insulating film IL2 is formed of thelow dielectric constant film has been explained. However, regarding theeffect of avoiding the reduction in the reliability between the wiringW1 and the gate electrode G1, it is not always required to form theinsulating film IL2 by the low dielectric constant film. In this case,the insulating film IL2 can be formed of, for example, a silicon oxidefilm as an insulating film.

In the third embodiment, as similar to the above-described first andsecond embodiments, the above-described effect can be obtained byforming the upper surface of the plug PL1 so as to be even slightlyhigher than the upper surface of the insulating film SO. Here, a morepreferable condition used when the plug PL1 and the wiring W1 are formedwill be explained.

FIG. 38 is an enlarged cross-sectional view of a principal part (apartially-enlarged cross-sectional view) of an enlarged periphery of aregion where the plug PL1 and the wiring W1 are connected to each otherin FIG. 34. Hereinafter, with reference to FIG. 38, a more preferablecondition for the formation of the plug PL1 and the wiring W1 will beexplained.

As illustrated in FIG. 38, a distance from the lowermost surface of thewiring W1 to the upper surface of the plug PL1 is set as a length L8.Meanwhile, a distance from the upper surface of the insulating film SOto the lowermost surface of the wiring W1 is set as a length L9. Here,in the third embodiment, the length L8 corresponds to theabove-described length L1 (that is, “L8=L1”). Note that, for easilyunderstanding, in FIG. 38, the upper surface of the insulating film SOis provided with a reference symbol SOSF so as to be represented as anupper surface SOSF of the insulating film SO, the upper surface of theplug PL1 is provided with a reference symbol PLSF so as to berepresented as an upper surface PLSF of the plug PL1, and the lowermostsurface of the wiring W1 is provided with a reference symbol W1SF so asto be represented as the lowermost surface W1SF of the wiring W1.

At this time, it is desired that a relation of “L8>L9” is establishedbetween the length L8 and the length L9 (that is, it is desired that thelength L8 is larger than the length L9). By forming the plug PL1 and thewiring W1 so as to establish the relation of “L8>L9”, the whole wiringW1 can be formed inside the insulating film IL2 which is the lowdielectric constant film so that the receding amount of the insulatingfilm SO is not increased in the step of making the insulating film SOillustrated in the above-described FIG. 35 to recede, and besides, thatthe connection between the plug PLI1 and the wiring W1 in the directionperpendicular to the semiconductor substrate 1S is ensured in a laterstep. In the step illustrated in FIG. 35, if a receding distance of theinsulating film SO is too large, controllability and repeatability ofthe etching of the insulating film SO or the polishing thereof isreduced accordingly, and therefore, this is not preferable. Therefore,it is preferred to suppress the receding distance as small as possible,and therefore, it is preferred to apply the above-described condition(the relation of “L8>L9”). More particularly, by shortening the lengthL9 as short as possible, the receding amount of the upper surface of theinsulating film SO in the step illustrated in FIG. 35 is decreased, andtherefore, the characteristics of the semiconductor device can bestabilized without the reduction in the controllability andrepeatability in the step of making the insulating film SO to recede.Also, as different from the above-described first and secondembodiments, the whole wiring W1 is formed inside the insulating filmIL2 which is the low dielectric constant film in the third embodiment,and therefore, the inter-wiring capacitance can be effectively reduced.In the third embodiment, by setting relations of, for example, “L8=30nm” and “L9=5 nm”, the above-described condition (relation of “L8>L9”)is satisfied.

Steps after that (after the formation of the wiring W1) are similar tothose of the above-described first embodiment so as to form asecond-layer wiring. However, illustration and explanation thereof areomitted here.

Also in the third embodiment, as similar to the above-described firstand second embodiments, the explanation has been made based on the casethat the diameter of the upper surface of the plug PL1 and the width ofthe lower surface of the wiring are formed so as to be almost equal toeach other. However, their relation is not limited to such a case, and acase that the diameter of the plug PL1 is larger than the width of thelower surface of the wiring W1 and a case that the diameter of the plugPL1 is smaller than the width of the lower surface of the wiring can bealso applied.

According to the third embodiment, after the polishing for forming theplug PL1 ends, the upper surface (the surface) of the insulating film SOis made to recede so that the upper surface of the plug PL1 is higherthan the upper surface of the insulating film SO. By making the uppersurface (the surface) of the insulating film SO to recede, theconnection between the plug PL1 and the wiring W1 in the directionperpendicular to the semiconductor substrate 1S can be ensured even ifthe wiring W1 to be formed later is not embedded inside the insulatingfilm SO. Further, by forming the wiring W1 so as not to be embeddedinside the insulating film SO, the surface area of the wiring W1 formedinside the insulating film IL2 which is the low dielectric constant filmis increased, and therefore, the increase in the inter-wiringcapacitance can be avoided even if the microfabrication of the wiringstructure is achieved. Still further, by forming the interlayerinsulating film WIL1 by one layer of the insulating film IL2, the wholewiring W1 is formed inside the insulating film IL2 which is the lowdielectric constant film, and therefore, the inter-wiring capacitancecan be further effectively reduced.

Fourth Embodiment

In the above-described third embodiment, the interlayer insulating filmWIL1 is formed of one layer of the insulating film IL2 without formingthe insulating film IL1 as a part of the interlayer insulating film WIL,and the whole wiring W1 is formed inside the insulating film IL2. In afourth embodiment, the formation of the interlayer insulating film WIL1by one layer of the insulating film IL2 is similar to that of theabove-described third embodiment, but the wiring W1 is formed not onlyinside the insulating film IL2 but also inside the interlayer insulatingfilm SO. That is, the lowermost surface of the wiring W1 is formedinside the insulating film SO.

FIG. 39 is a cross-sectional view of a principal part of a semiconductordevice according to the fourth embodiment, and illustrates a crosssection corresponding to the cross section A (the cross section takenalong the line A-A) illustrated in the above-described FIG. 2 of theabove-described first embodiment.

As illustrated in FIG. 39, in the semiconductor device according to thefourth embodiment, as similar to the semiconductor devices of theabove-described first to third embodiments, the upper surface of theplug PL1 is formed higher than the upper surface of the insulating filmSO, that is, the upper surface of the interlayer insulating film PIL.Also, in the semiconductor device according to the fourth embodiment, assimilar to the above-described third embodiment, the insulating film IL1is not formed, and the interlayer insulating film WIL1 is formed of onelayer of the insulating film IL2. Further, in the semiconductor deviceaccording to the fourth embodiment, as similar to the above-describedfirst embodiment, the wiring W1 is formed not only inside the interlayerinsulating film WIL1 but also inside the insulating film SO, that is,the interlayer insulating film PIL. That is, the lowermost surface ofthe wiring W1 is formed inside the insulating film SO, that is, theinterlayer insulating film PIL.

In the fourth embodiment, by forming the plug PL1 so as to protrude fromthe upper surface of the insulating film SO, that is, the upper surfaceof the interlayer insulating film PIL, the connection between the plugPL1 and the wiring W1 can be ensured even if an embedding amount of thewiring W1 inside the insulating film SO, that is, the interlayerinsulating film PIL is decreased. Also, by decreasing the embeddingamount of the wiring trench WT1 inside the insulating film SO, that is,the interlayer insulating film PIL, the surface area of the wiring W1which is formed inside the insulating film IL2 which is the lowdielectric constant film is increased. Therefore, for example, theinter-wiring capacitance between the wirings W1 can be reduced. In thefourth embodiment, since the interlayer insulating film WIL1 is formedof one layer of the insulating film IL2 which is the low dielectricconstant film, the effect of reducing the inter-wiring capacitance canbe expected further than the above-described first embodiment.

Hereinafter, a method of manufacturing the semiconductor deviceaccording to the fourth embodiment will be explained with reference tothe drawings. Each of FIGS. 40 to 42 is a cross-sectional view of aprincipal part of the semiconductor device of the fourth embodiment in amanufacturing step, and illustrates a cross section corresponding to theabove-described cross section A.

The steps illustrated in the above-described FIGS. 4 to 8 of theabove-described first embodiment also similarly performed in the fourthembodiment.

Note that, also in the fourth embodiment, in the following steps, anupper surface of the insulating film SO is synonymously used with anupper surface of the interlayer insulating film PIL, and an inside ofthe insulating film SO is synonymously used with an inside of theinterlayer insulating film PIL.

After the step illustrated in the above-described FIG. 8 of theabove-described first embodiment, the upper surface of the insulatingfilm SO is made to recede in the fourth embodiment as illustrated inFIG. 40. A receding amount of the upper surface of the insulating filmSO is, for example, 25 nm. As described in the above-described firstembodiment, the method of making the insulating film SO to recede can beperformed by dry etching, wet etching, or a CMP method by using apolishing liquid having a high selectivity for the insulating film SO.After the insulating film SO is made to recede, the upper surface of theinsulating film SO is lower than the upper surface of the plug PL1 asillustrated in FIG. 40. That is, the upper surface (the surface) of theinsulating film SO is made to recede so that the plug PL1 protrudes fromthe upper surface of the insulating film SO.

Next, a first-layer wiring is formed by a single damascene method.Hereinafter, a method of forming the first-layer wiring will beexplained.

First, as illustrated in FIG. 41, the insulating film IL2 is formed onthe interlayer insulating film PIL (the insulating film SO) and on theplug PL1. The insulating film IL2 is formed on the interlayer insulatingfilm PIL (the insulating film SO) so as to cover a portion of the plugPL1 protruding from the upper surface of the interlayer insulating filmPIL (the insulating film SO). The insulating film IL2 is formed of, forexample, a SiOC film as a low dielectric constant film in order toreduce the inter-wiring capacitance. A thickness of the insulating filmIL2 is, for example, 85 nm.

In the fourth embodiment, as similar to the above-described thirdembodiment, it is assumed when there is no risk of the abnormalelectrical discharge upon the formation of the SiOC film, when there isno requirement to form the insulating film IL2 by a low dielectricconstant film other than the SiOC film or others so as to prevent theabnormal electrical discharge, or when there is no requirement to formthe insulating film IL1 even as the etching stopper. Therefore, also inthe fourth embodiment, the insulating film IL1 is not formed before theformation of the insulating film IL2, the interlayer insulating filmWIL1 is formed of one layer of the insulating film IL2, and theinsulating film IL2 indicates the interlayer insulating film WIL1 in thefollowing steps.

Next, as illustrated in FIG. 42, the wiring trench WT1 is formed in theinsulating film IL2. Because of the wiring trench WT1, at least a partof the upper surface (the upper portion) of the plug PL1 and a part ofthe side surfaces thereof are exposed. A depth of the wiring trench WT1is, for example, 90 nm. The lowermost surface of the wiring trench WT1is formed inside the insulating film SO. That is, the wiring trench WT1is formed inside the insulating film IL2 and inside the insulating filmSO. The lowermost surface of the wiring trench WT1 is positioned lowerthan the upper surface of the plug PL1, and besides, for example, 5 nmlower than the upper surface of the insulating film SO. In the fifthembodiment, since the lowermost surface of the wiring trench WT1 isformed inside the insulating film SO, the lowermost surface of thewiring trench WT1 is formed of the exposed surface of the insulatingfilm SO, and the lowermost surface of the wiring W1 to be buried in thiswiring trench WT1 later is in contact with this exposed surface of theinsulating film SO. Note that FIG. 42 illustrates a case that the wiringtrench WT1 is formed at a position shifted from the plug PL1 in adirection parallel to the cross section A as similar to theabove-described FIG. 19 in the above-described first embodiment.

As described in the above-described first embodiment, in order to formthe wiring trench WT1, the insulating film IL2 is dry-etched by using aphotoresist pattern (a patterned photoresist film) formed by aphotolithography technique as a mask (an etching mask). In this etchingstep, an etching endpoint of the insulating film IL2 is detected in, forexample, a scribe region at the time when the etching of the insulatingfilm IL2 reaches the surface of the insulating film SO (that is, at thetime when a part of the surface of the insulating film SO is exposed).In the fourth embodiment, the insulating film IL2 is formed of the SiOCfilm as the low dielectric constant film, the insulating film SO isformed of the silicon oxide film as the insulating film, and theinsulating film IL2 and the insulating film SO are formed of differentmaterials (insulating materials) from each other, and therefore, theetching endpoint can be detected at a boundary between the insulatingfilm IL2 and the insulating film SO. Even after the endpoint isdetected, the etching for a predetermined time (a certain time) (theetching of the insulating film SO) is performed similarly to theabove-described first embodiment, so that the wiring trench WT1 iscompleted. Finally, at least a part of the upper surface (the upperportion) of the plug PL1 and a part of the side surfaces thereof areexposed because of the wiring trench WT1.

Therefore, the step of forming the wiring trench WT1 includes: a firststep of etching the insulating film IL2; a second step of detecting theetching endpoint of the insulating film IL2 when the etching in thefirst step reaches the upper surface of the insulating film SO; and athird step of etching the insulating film SO after the second step.

In this manner, in the process of the dry etching for forming the wiringtrench WT1, the wiring trench WT1 is formed by dividing the dry etchingstep into two stages (the first step and the third step) by the endpointdetection, so that it can be avoided to form the lowermost surface ofthe wiring trench WT1 at a position close to the gate electrode G1 ofthe n-channel-type MISFET Q₁ due to the excessively-performed etching.Also, the processing accuracy of the etching can be improved.

Also, if the insulating film IL2 or the insulating film SO remains onthe side surfaces of the plug PL1 to be exposed from the wiring trenchWT1 after this dry etching (that is, after the dry-etching step forforming the wiring trench WT1), it is preferred to further perform wetetching or others after this dry etching so as to remove the insulatingfilm IL2 or the insulating film SO remaining on the side surfaces of theplug PL1 and expose the side surfaces of the plug PL1 from the wiringtrench WT1. In this manner, the exact connection between the wiring W1to be formed in a later step and the plug PL1 can be ensured.

Also in the fourth embodiment, since the insulating film SO is made torecede by the step illustrated in FIG. 40, the upper surface of the plugPL1 is formed at a position higher than the upper surface of theinsulating film SO. On the other hand, the lowermost surface of thewiring trench WT1 is formed inside the insulating film SO, and besides,the lowermost surface of the wiring trench WT1 is formed at a positionlower than the upper surface of the plug PL1. Therefore, at least a partof the upper surface of the plug PL1 and a part of the side surfaces ofthe plug PL1 are exposed because of the wiring trench WT1, so that, whena conductive film is buried in the wiring trench WT1 in a later step,the conductive film buried in this wiring trench WT1 and the plug PL1can be reliably connected to each other.

Next, as similar to the above-described first embodiment, the wiring W1is formed as illustrated in the above-described FIG. 39 by forming thebarrier conductor film WBM on the insulating film IL2 including theportion on the inner wall (the side surfaces and the bottom portion) ofthe wiring trench WT1, forming the conductor film CUF on the barrierconductor film WBM so as to be buried (be filled) inside the wiringtrench WT1, and then, polishing and removing unnecessary portions of theconductor film CUF and the barrier conductor film WBM formed outside thewiring trench WT1 by using a CMP method. The wiring W1 is formed of theconductor film CUF and the barrier conductor film WBM buried andremaining inside the wiring trench WT1. A depth of the wiring W1 issimilar to a depth of the wiring trench WT1, which is, for example, 90nm. Also, a position of the lowermost surface of the wiring W1 issimilar to a position of the lowermost surface of the wiring trench WT1as illustrated in FIG. 42.

The wiring trench WT1 is formed inside the insulating film IL2 and theinsulating film SO, that is, the lowermost surface of the wiring trenchWT1 is formed inside the insulating film SO, and therefore, the wiringW1 formed by burying the barrier conductor film WBM and the conductorfilm CUF in the wiring trench WT1 is also formed inside the insulatingfilm IL2 and the insulating film SO, and the lowermost surface of thewiring W1 is formed inside the insulating film SO. Further, asillustrated in the above-described FIG. 39, the upper surface of theplug PL1 is formed at a position higher than the upper surface of theinsulating film SO, and besides, the lowermost surface of the wiring W1is formed at a position lower than the upper surface of the plug PL1,and therefore, at least each of a part of the upper surface of the plugPL1 and a part of the side surfaces thereof are covered with the wiringW1. In this manner, the connection between the plug PL1 and the wiringW1 can be ensured, so that the reliability of the connection between theplug PL1 and the wiring W1 can be improved.

Further, in the fourth embodiment, the wiring W1 is formed even insidethe insulating film SO as similar to the above-described firstembodiment. However, as different from the above-described firstembodiment, the interlayer insulating film WIL1 is formed of one layerof the insulating film IL2. Therefore, the ratio of the portion of thewiring W1 which is formed inside the insulating film IL2 which is thelow dielectric constant film is larger in the fourth embodiment thanthat in the case that the interlayer insulating film WIL1 is formed oftwo layers of the insulating film IL1 and the insulating film IL2.Therefore, the inter-wiring capacitance can be further effectivelyreduced in the fourth embodiment than the above-described firstembodiment.

On the other hand, in the above-described third embodiment, the wholewiring W1 is formed inside the insulating film IL2 which is the lowdielectric constant film, and therefore, the inter-wiring capacitancecan be further effectively reduced than the fourth embodiment. However,in the above-described third embodiment, in order to form the wholewiring W1 inside the insulating film IL2, it is required to increase thereceding amount of the insulating film SO in the step of theabove-described FIG. 35 so as to be larger than that of the fourthembodiment in consideration of the need of ensuring the connectionbetween the plug PL1 and the wiring W1 in the direction perpendicular tothe semiconductor substrate 1S. On the other hand, if the structure asdescribed in the fourth embodiment is used, the connection between theplug PL1 and the wiring W1 in the direction perpendicular to thesemiconductor substrate 1S is ensured by forming a part of the wiring W1even inside the insulating film SO, and therefore, the receding amountof the insulating film SO in the step of FIG. 42 can be smaller thanthat of the above-described third embodiment. Therefore, in the fourthembodiment, controllability of the step of making the insulating film SOto recede (the step of FIG. 42) and repeatability thereof are increased,so that the characteristics of the semiconductor element can bestabilized.

Also, in the fourth embodiment, by forming the upper surface of the plugPL1 so as to be higher than the upper surface of the insulating film SO,the length L1 by which the wiring W1 and the plug PL1 are overlappedwith each other in the direction perpendicular to the semiconductorsubstrate 1S can be ensured even if the wiring W1 is not embedded insidethe insulating film SO deeper than that in the case of the manufacturingstep of the above-described comparative example. Therefore, even if themicrofabrication of wirings is achieved, the increase in theinter-wiring capacitance between the wirings W1 due to the increase inthe ratio of the portion of the wiring W1 which is formed inside theinsulating film SO can be avoided.

Further, in the fourth embodiment, by avoided the formation of thelowermost surface of the wiring trench WT1 at the position close to thegate electrode G1 of the n-channel-type MISFET Q₁, the shortening of thedistance between the wiring W1 and the gate electrode G1 can be avoided,so that the reduction in the reliability between the wiring W1 and thegate electrode G1 can be avoided. In the fourth embodiment, the casethat the insulating film IL2 is formed of the low dielectric constantfilm has been explained. However, regarding the effect of avoiding thereduction in the reliability between the wiring W1 and the gateelectrode G1, it is not always required to form the insulating film IL2by the low dielectric constant film. In this case, the insulating filmIL2 can be formed of, for example, a silicon oxide film as an insulatingfilm.

In the fourth embodiment, as similar to the above-described first andthird embodiments, the above-described effect can be obtained by formingthe upper surface of the plug PL1 so as to be even slightly higher thanthe upper surface of the insulating film SO. Here, a more preferablecondition used when the plug PL1 and the wiring W1 are formed will beexplained.

FIG. 43 is an enlarged cross-sectional view of a principal part (apartially-enlarged cross-sectional view) of an enlarged periphery of aregion where the plug PL1 and the wiring W1 are connected to each otherin FIG. 39. Hereinafter, with reference to FIG. 43, a more preferablecondition for the formation of the plug PL1 and the wiring W1 will beexplained.

As illustrated in FIG. 43, a distance from the upper surface of theinsulating film SO to the upper surface of the plug PL1 is set as alength L10. Meanwhile, a distance from the lowermost surface of thewiring W1 to the upper surface of the insulating film SO is set as alength L11. Here, in the fourth embodiment, addition of the length L10and the length L11 corresponds to the above-described length L1 (thatis, “L1=L10+L11”). Note that, for easily understanding, in FIG. 43, theupper surface of the insulating film SO is provided with a referencesymbol SOSF so as to be represented as an upper surface SOSF of theinsulating film SO, the upper surface of the plug PL1 is provided with areference symbol PLSF so as to be represented as an upper surface PLSFof the plug PL1, and the lowermost surface of the wiring W1 is providedwith a reference symbol W1SF so as to be represented as the lowermostsurface W1SF of the wiring W1.

At this time, it is desired that a relation of “L10>L11” is establishedbetween the length L10 and the length L11 (that is, it is desired thatthe length L10 is larger than the length L11). By forming the plug PL1and the wiring W1 so as to establish the relation of “L10>L11”, theconnection between the plug PL1 and the wiring W1 in the directionperpendicular to the semiconductor substrate 1S can be ensured asavoiding the increase in the forming amount of the wiring W1 so as to beembedded inside the insulating film SO (that is, an amount correspondingto the length L11). Also, by avoiding the increase in the embeddingamount of the wiring W1 inside the insulating film SO (that is, theamount corresponding to the length L11), the ratio of the portion of thewiring W1 which is formed inside the insulating film IL2 which is thelow dielectric constant film is increased. In other words, by avoidingthe increase in the embedding amount of the wiring W1 inside theinsulating film SO (that is, the amount corresponding to the lengthL11), an area where the wiring W1 and the insulating film IL2 which isthe low dielectric constant film are in contact with each other can beincreased. Therefore, for example, the inter-wiring capacitance betweenadjacent wirings W1 can be reduced. Also, by avoiding the formation ofthe lowermost surface of the wiring W1 at the position close to the gateelectrode G1 of the n-channel-type MISFET Q₁ the reduction in thereliability between the wiring W1 and the gate electrode G1 can beavoided. More particularly, by shortening the length L11 as small aspossible, the forming amount of the wiring W1 inside the insulating filmSO (that is, the amount corresponding to the length L11) can bedecreased, and therefore, the inter-wiring capacitance can be furthereffectively reduced, and the reduction in the reliability between thewiring W1 and the gate electrode G1 can be avoided. In the fourthembodiment, by setting relations of, for example, “L10=25 nm” and “L11=5nm”, the above-described condition (the relation of “L10>L11”) issatisfied.

Steps after that (after the formation of the wiring W1) are similar tothose of the above-described first embodiment so as to form asecond-layer wiring. However, illustration and explanation thereof areomitted here.

Also in the fourth embodiment, as similar to the above-described firstto third embodiments, the explanation has been made based on the casethat the diameter of the upper surface of the plug PL1 and the width ofthe lower surface of the wiring are formed so as to be almost equal toeach other. However, their relation is not limited to such a case, and acase that the diameter of the plug PL1 is larger than the width of thelower surface of the wiring W1 and a case that the diameter of the plugPL1 is smaller than the width of the lower surface of the wiring W1 canbe also applied.

According to the fourth embodiment, after the polishing for forming theplug PL1 ends, the surface of the insulating film SO is made to recedeso that the upper surface of the plug PL1 is higher than the uppersurface of the insulating film SO. By making the surface of theinsulating film SO to recede, even if the embedding amount of the wiringW1 to be formed inside the insulating film SO later is decreased furtherthan that in the case of the manufacturing step of the above-describedcomparative example, the connection between the plug PL1 and the wiringW1 in the direction perpendicular to the semiconductor substrate 1S canbe ensured. Further, by decreasing the embedding amount of the wiring W1inside the insulating film SO, the surface area of the wiring W1 to beformed inside the insulating film IL2 which is the low dielectricconstant film is increased, and therefore, the increase in theinter-wiring capacitance can be avoided even if the microfabrication ofthe wiring structure is achieved. Still further, by forming theinterlayer insulating film WIL1 by one layer of the insulating film IL2,the surface area of the wiring W1 to be formed inside the insulatingfilm IL2 which is the low dielectric constant film is further increased,and therefore, the inter-wiring capacitance can be further effectivelyreduced.

Fifth Embodiment

In the above-described first to fourth embodiments, the interlayerinsulating film PIL is formed of the insulating film SN and theinsulating film SO thereon, and the insulating film SO may be formed ofany of an O₃-TEOS film, a P-TEOS film, and a stacked film of the O₃-TEOSfilm and the P-TEOS film. On the other hand, in a fifth embodiment, theinsulating film SO is formed of the stacked film of the O₃-TEOS film andthe P-TEOS film thereon.

FIG. 44 is a cross-sectional view of a principal part of a semiconductordevice according to the fifth embodiment, and illustrates a crosssection corresponding to the cross section A (the cross section takenalong the line A-A) illustrated in the above-described FIG. 2 of theabove-described first embodiment.

In the semiconductor device of the present embodiment illustrated inFIG. 44, the interlayer insulating film PIL is formed of the insulatingfilm SN and the insulating film SO thereon, and this silicon oxide filmSO is formed of a stacked film of an O₃-TEOS film OTS and a P-TEOS filmPTS. The semiconductor device in the fifth embodiment has a structuresimilar to that of the semiconductor device in the above-described firstembodiment except that the silicon oxide film SO is formed of thestacked film of the O₃-TEOS film OTS and the P-TEOS film PTS, andtherefore, repetitive description thereof is omitted here.

Hereinafter, a method of manufacturing the semiconductor deviceaccording to the fifth embodiment will be explained with reference tothe drawings. Each of FIGS. 45 to 49 is a cross-sectional view of aprincipal part of the semiconductor device of the fifth embodiment in amanufacturing step, and illustrates a cross section corresponding to theabove-described cross section A.

The steps up to the one illustrated in the above-described FIG. 4 of theabove-described first embodiment also similarly performed in the fifthembodiment.

After the step illustrated in the above-described FIG. 4 of theabove-described first embodiment, in the fifth embodiment, theinsulating film SN is formed on the semiconductor substrate 1S in whichthe n-channel-type MISFET Q₁ is formed as illustrated in FIG. 45. Thatis, the insulating film SN is formed on the semiconductor substrate 1Sincluding a portion on the metal silicide layer NSF1 so as to cover thegate electrode G1 and the side walls SW1. As similar to theabove-described first embodiment, the insulating film SN is formed of asilicon nitride film as an insulating film.

Then, in the fifth embodiment, the O₃-TEOS film OTS is formed on theinsulating film SN. A reason why the O₃-TEOS film OTS is formed that theO₃-TEOS film OTS is preferable as a film to be buried betweensemiconductor elements such as the n-channel-type MISFETs Q₁ (forexample, between adjacent gate electrodes) formed on the semiconductorsubstrate 1S because the O₃-TEOS film OTS indicates excellent fluidity.However, the O₃-TEOS film has a slow growth rate and a weak mechanicalstrength. Therefore, in the fifth embodiment, after the O₃-TEOS film OTSis buried between semiconductor elements (for example, between adjacentgate electrodes), the P-TEOS film PTS having a stronger mechanicalstrength and lower moisture absorption characteristics than those of theO₃-TEOS film OTS is formed on the O₃-TEOS film OTS. The P-TEOS film PTShas a lower fluidity than that of the O₃-TEOS film OTS, and therefore,is formed so as to have an almost uniform thickness along a shape of theO₃-TEOS film OTS which is a base film. Therefore, as illustrated in FIG.45, when the P-TEOS film PTS is formed, the P-TEOS film PTS formed abovethe semiconductor element such as the n-channel-type MISFET Q₁ isswelled. In the fifth embodiment, for example, a depositing thickness ofthe O₃-TEOS film OTS is 45 nm, and a depositing thickness of the P-TEOSfilm PTS is 100 nm.

Next, as illustrated in FIG. 46, a surface (an upper surface) of theP-TEOS film PTS is polished by using a CMP method so as to beplanarized. In this polishing, at the stage of the end of the polishing,it is required that the P-TEOS film PTS having a certain thicknessremains above the semiconductor element such as the n-channel-typeMISFET Q₁. This is because of the following reason. That is, the O₃-TEOSfilm has an excellent filling performance but higher moisture absorptioncharacteristics (is easier to absorb moisture) than that of the P-TEOSfilm, and has a high moisture content at the stage of film formation,and therefore, tends not to be excellent in an insulation property. Thatis, it can be said that the O₃-TEOS film OTS is an insulating filmhaving higher moisture absorption characteristics than that of theP-TEOS film PTS, and the P-TEOS film PTS is an insulating film havinglower moisture absorption characteristics than that of the O₃-TEOS filmOTS. Therefore, if the P-TEOS film PTS formed on the n-channel-typeMISFET Q₁ is too thin or is totally polished, when the wiring W1 (thefirst-layer wiring) is formed inside the interlayer insulating film (theinterlayer insulating film WIL1) of the first-layer wiring, there is arisk that a distance between the wiring W1 and the O₃-TEOS film OTSbecomes close to each other or the wiring W1 and the O₃-TEOS film OTSbecomes in contact with each other, which results in the reduction inthe reliability of the wiring W1 with respect to the O₃-TEOS film OTS.Therefore, in this step (the step of polishing the P-TEOS film PTS), itis required to set the thickness of the P-TEOS film PTS to be depositedand set the polishing amount of the P-TEOS film PTS to be subsequentlyperformed so that the P-TEOS film PTS having a desired thickness remainseven after the polishing on the semiconductor element such as then-channel-type MISFET Q₁.

While the interlayer insulating film PIL is formed of the insulatingfilm SN and the insulating film SO thereon, the insulating film SO isformed of the O₃-TEOS film OTS and the P-TEOS film PTS formed thereon inthe fifth embodiment. Therefore, in the following steps, an uppersurface of the P-TEOS film PTS is synonymously used with an uppersurface of the insulating film SO or an upper surface of the interlayerinsulating film PIL, and an inside of the P-TEOS film PTS issynonymously used with an inside of the interlayer insulating film PILor an inside of the insulating film SO.

Next, as similar to the step illustrated in the above-described FIG. 6of the above-described first embodiment, the interlayer insulating filmPIL is dry-etched by using a photoresist pattern (a patternedphotoresist film) formed on the interlayer insulating film PIL by aphotolithography technique as a mask (an etching mask) as illustrated inFIG. 47, so that the contact hole CNT1 is formed in the interlayerinsulating film PIL. Then, as similar to the step illustrated in theabove-described FIG. 7 of the above-described first embodiment, thebarrier conductor film PBM is formed on the interlayer insulating filmPIL including inner walls (side surfaces and a bottom portion) of thecontact hole CNT1 as illustrated in FIG. 47. Subsequently, the conductorfilm TF is formed on the barrier conductor film PBM. The contact holeCNT1 is filled with the barrier conductor film PBM and the conductorfilm TF.

Next, as similar to the steps illustrated in the above-described FIGS. 8and 9 of the above-described first embodiment, unnecessary portions ofthe conductor film TF and the barrier conductor film PBM formed outsidethe contact hole CNT1 are removed so as to form the plug PL1, and then,the upper surface of the P-TEOS film PTS is made to recede so that theupper surface of the P-TEOS film PTS is lower than the upper surface ofthe plug PL1 as illustrated in FIG. 48. That is, the upper surface ofthe P-TEOS film PTS is made to recede so that the upper surface of theplug PL1 protrudes from the upper surface of the P-TEOS film PTS. Alsoin the fifth embodiment as similar to the above-described firstembodiment, as the method of making the upper surface of the P-TEOS filmPTS (the interlayer insulating film PIL) to recede, dry etching, wetetching, or polishing by a CMP method may be applied as long as theupper surface of the P-TEOS film PTS can be selectively made to recedefrom the plug PL1. Also in this step (the step of making the uppersurface of the P-TEOS film PTS to recede), it is required that theP-TEOS film PTS having a desired thickness remains on the semiconductorelement such as the re-channel-type MISFET Q₁ when the upper surface ofthe P-TEOS film PTS is made to recede. This is for avoiding thereduction in the reliability of the wiring W1 due to the O₃-TEOS filmOTS.

Next, as similar to the step illustrated in the above-described FIG. 10of the above-described first embodiment, the insulating film IL1 and theinsulating film IL2 are formed as the interlayer insulating film WIL1 ofthe first-layer wiring as illustrated in FIG. 49. The insulating filmIL2 is formed as a low dielectric constant film. In the fifthembodiment, the insulating film IL1 is formed. However, as in theabove-described third and fourth embodiments, if it is not required toform the insulating film IL1, the interlayer insulating film WIL1 can beformed of one layer of the insulating film IL2 which is the lowdielectric constant film.

Next, as similar to the steps illustrated in FIGS. 19, 20, and 21A ofthe above-described first embodiment, the wiring W1 is formed asillustrated in the above-described FIG. 44 by forming the wiring trenchWT1 inside the interlayer insulating film WIL1, forming the barrierconductor film WBM and the conductor film CUF so as to be buried insidethe wiring trench WT1, and removing unnecessary portions of the barrierconductor film WBM and the conductor film CUF by using a CMP method.

In the step illustrated in FIG. 48, since the upper surface of theP-TEOS film PTS is made to recede so that the upper surface of the plugPL1 is higher than the upper surface of the P-TEOS film PTS, theembedding amount of the wiring W1 inside the insulating film SO can bedecreased further than that in the case of the manufacturing step of theabove-described comparative example even if the wiring W1 is formed sothat the connection between the plug PL1 and the wiring W1 in thedirection perpendicular to the semiconductor substrate 1S is ensured bythe length L1. Therefore, the wiring W1 can be formed in the state thatthe distance between the wiring W1 and the O₃-TEOS film OTS is notshortened, and therefore, the reduction in the reliability of the wiringW1 due to the O₃-TEOS film OTS can be avoided. Further, in the fifthembodiment, when the wiring trench WT1 is formed, the etching with usingthe endpoint detection is performed as described in the above-describedfirst embodiment, and therefore, it is possible to avoid the formationof the lowermost surface of the wiring trench WT1 at a position close tothe gate electrode G1 of the n-channel-type MISFET Q₁ due to theexcessively-large etching amount of the P-TEOS film PTS. As a result,the formation of the wiring W1 at a position close to the gate electrodeG1 can be avoided, so that the reduction in the reliability between thegate electrode G1 and the wiring W1 can be avoided.

In the fifth embodiment, the case that the insulating film SO formingthe interlayer insulating film PIL in the above-described firstembodiment is further formed of the O₃-TEOS film OTS and the P-TEOS filmPTS formed thereon has been explained, and therefore, the effect ofavoiding the reduction in the reliability of the wiring W1 due to theO₃-TEOS film OTS can be obtained, and besides, the effects similar tothe effects described in the above-described first embodiment can beobtained.

Further, in the fifth embodiment, the case that the insulating film IL2is formed of the low dielectric constant film has been explained.However, regarding the effect of avoiding the reduction in thereliability between the wiring W1 and the gate electrode G1 or avoidingthe reduction in the reliability between the wiring W1 and the O₃-TEOSfilm OTS, it is not always required to form the insulating film IL2 bythe low dielectric constant film. In this case, the insulating film IL2can be formed of, for example, a silicon oxide film as an insulatingfilm.

By also configuring the preferable condition used when the plug PL1 andthe wiring W1 are formed as the condition similar to that of theabove-described first embodiment, the effects similar to those of theabove-described first embodiment can be obtained, and besides, thereduction in the reliability between the O₃-TEOS film OTS and the wiringW1 can be avoided.

Steps after that (after the formation of the wiring W1) are similar tothose of the above-described first embodiment so as to form asecond-layer wiring. However, illustration and explanation thereof areomitted here.

In the fifth embodiment, the case that the semiconductor deviceaccording to the fifth embodiment is manufactured in line with themanufacturing steps of the above-described first embodiment has beenexplained. However, the fifth embodiment can be also applied to not onlythe case that the insulating film SO of the above-described firstembodiment is formed of the stacked film of the O₃-TEOS film OTS and theP-TEOS film PTS but also the case that the insulating film SO is formedof the stacked film of the O₃-TEOS film OTS and the P-TEOS film in theabove-described second to fourth embodiments. When the insulating filmSO is formed of the stacked film of the O₃-TEOS film OTS and the P-TEOSfilm thereon in the above-described second to fourth embodiments, theabove-described effects in the above-described second to fourthembodiments can be obtained, and besides, the effect of avoiding thereduction in the reliability of the wiring W1 due to the O₃-TEOS filmOTS can be obtained.

Sixth Embodiment

In the above-described first to fifth embodiments, a wiring width of thefirst-layer wiring (the wiring W1) is one type. On the other hand, in asixth embodiment, the wiring width of the first-layer wiring (wirings W1and W1 a) is two types or more. Here, the wiring width refers to a width(a dimension in a direction parallel to a main surface of thesemiconductor substrate 1S) of a wiring obtained to be cut in adirection perpendicular to a direction of current flow.

The sixth embodiment will be explained below as a case that wiringshaving different wiring widths from each other are formed in addition tothe first embodiment. Therefore, while the explanation has been made inthe above-described first embodiment with reference to only the crosssection A, explanations of a semiconductor device according to the sixthembodiment and a method of manufacturing the same have been explained inthe sixth embodiment with reference to not only the cross section A butalso a cross-sectional view taken along the line C-C illustrated in theabove-described FIG. 2. Hereinafter, a cross section taken along theline C-C illustrated in the above-described FIG. 2 is referred to as across section C.

FIG. 50 is cross-sectional views of principal parts of the semiconductordevice according to the sixth embodiment, and illustrates not only thecross section A (the cross section taken along the line A-A) of theabove-described first embodiment illustrated in the above-described FIG.3 but also a cross-sectional view of the cross section C (across-sectional view taken along the line C-C). In FIG. 50, a structureof the semiconductor device illustrated in the cross-sectional view ofthe cross section A (the cross section taken along the line A-A) issimilar to a structure of the semiconductor device of theabove-described first embodiment, and therefore, explanation thereof isomitted.

Hereinafter, the structure of the semiconductor device illustrated inthe cross-sectional view of the cross section C (the cross-sectionalview taken along the line C-C) in FIG. 50 will be explained.

In the cross section C, as illustrated in FIG. 50, an end portion of thegate electrode G1 of the n-channel-type MISFET Q₁ formed in the crosssection A is formed on the element isolation region STI, and the metalsilicide layer (the metal silicide film) NSF1 is formed above the gateelectrode G1. Also, a p-type semiconductor region PS2 is formed so as tobe interposed between the element isolation regions STI, and the metalsilicide layer NSF1 is formed above the p-type semiconductor region PS2.The p-type semiconductor region PS2 is formed inside a p-type well PWL1,and therefore, the p-type well PWL1 and the p-type semiconductor regionPS2 are electrically connected to each other. A plug PL1 a (and acontact hole PL1 a) is arranged above the metal silicide layer NSF1formed above the p-type semiconductor region PS2, and a bottom portionof this plug PL1 a is connected to the metal silicide layer NSF1 formedabove the p-type semiconductor region PS2. Via this plug PL1 a, apredetermined potential is supplied to the p-type semiconductor regionPS2 and the p-type well PWL1. Here, the plug PL1 a is a plug formed onthe same layer (the interlayer insulating film PIL) in the same step asthe plug PL1, and is formed inside the interlayer insulating film PIL.More specifically, a contact hole (through hole, hole) CNT1 a is formedin the interlayer insulating film PIL in the same step as the contacthole CNT1 a, and the plug PL1 a is formed inside this contact hole CNT1a in the same step as the plug PL1. As similar to the plug PL1, the plugPL1 a is also formed of the barrier conductor film PBM and the conductorfilm TF.

In the sixth embodiment, as described above, the wiring width of thefirst-layer wiring is configured of two types or more. FIG. 50illustrates the case that the wiring width of the first-layer wiring istwo types in which the width of the wiring W1 a is larger than the widthof the wiring W1. Here, the wiring W1 a is a wiring formed on the samelayer (the first-layer wiring) in the same step as the wiring W1. Notethat, for easily understanding, in the above-described FIGS. 2 and 24,the width of the wiring W1 a is provided with a reference symbol W1 aWso as to be represented as a width W1 aW of the wiring W1 a, the widthof the wiring W1 is provided with a reference symbol W1W so as to berepresented as a width W1W of the wiring W1, and the width W1 aW of thewiring W1 a is larger than the width W1W of the wiring W1 (that is, “W1aW>W1W”). In the sixth embodiment, a width (corresponding to the widthW1W) of an upper surface of the wiring W1 is, for example, 50 nm, and awidth (corresponding to the width W1 aW) of an upper surface of thewiring W1 a is, for example, 250 nm. As a wiring having a thick wiringwidth such as the wiring W1 a, a power supply wiring for supplying apower supply voltage is exemplified. The wiring W1 a is buried in thewiring trench WT1 a, and is a so-called buried wiring (a damascenewiring, a single damascene wiring). The plug PL1 a is partially exposedfrom the wiring trench WT1 a, and the plug PL1 a exposed from the wiringtrench WT1 a is in contact with and is electrically connected to thewiring W1 a buried in the wiring trench WT1 a. Therefore, the wiring W1a can be regarded as a buried wiring formed inside the interlayerinsulating film WIL1, and a buried wiring connected to the plug PL1 a.

Next, the depths of the wiring W1 and the wiring W1 a will be explained.As similar to the wiring W1, the lowermost surface of the wiring W1 a isformed inside the insulating film SO. However, as illustrated in FIG.50, the lowermost surface of the wiring W1 a is formed at a positionlower than the lowermost surface of the wiring W1. That is, a depth ofthe wiring W1 a is deeper than a depth of the wiring W1. The depth ofthe wiring W1 is, for example, 90 nm as similar to those of theabove-described first to fifth embodiments. On the other hand, the depthof the wiring W1 a is, for example, 105 to 110 nm.

Note that a lower surface (a bottom surface) of a portion of the wiringW1 which is not overlapped with the plug PL1 in plane forms thelowermost surface of the wiring W1, and, similarly, a lower surface (abottom surface) of a portion of the wiring W1 a which is not overlappedwith the plug PL1 a in plane forms the lowermost surface of the wiringW1 a. Also, a lower surface (a bottom surface) of a portion of thewiring trench WT1 which is not overlapped with the plug PL1 in planeforms the lowermost surface of the wiring trench WT1, and, similarly, alower surface (a bottom surface) of a portion of the wiring trench WT1 awhich is not overlapped with the plug PL1 a in plane forms the lowermostsurface of the wiring trench WT1 a.

On the other hand, as similar to the plug PL1, the upper surface of theplug PL1 a is formed at a position higher than the upper surface of theinsulating film SO (the interlayer insulating film PIL). Also, assimilar to the wiring W1 and the plug PL1, the lower surface of thewiring W1 a (more specifically, the lowermost surface of the wiring W1a) is formed at a position lower than the upper surface of the plug PL1a. In this manner, the connection between the plug PL1 a and the wiringW1 a can be ensured further than that of the manufacturing step of theabove-described comparative example even if the embedding amount of thewiring W1 a inside the insulating film SO is decreased. Also, byincrease in a surface area of the wiring W1 a formed inside theinsulating film IL2 which is the low dielectric constant film, theinter-wiring capacitance between the wiring W1 a and other wiring can bereduced.

FIG. 50 illustrates not only the length L1 which is a length of overlapof the plug PL1 with the wiring W1 in the cross section A in thedirection perpendicular to the semiconductor substrate 1S but also alength L1 a which is a length of overlap of the plug PL1 a with thewiring W1 a in the cross section C in the direction perpendicular to thesemiconductor substrate 1S. This length L1 a is also a distance from thelower surface of the wiring W1 a (more specifically, the lowermostsurface of the wiring W1) to the upper surface of the plug PL1 a.

The upper surface of the plug PL1 a and the upper surface of the plugPL1 are formed at almost the same height while the lowermost surface ofthe wiring W1 a is formed at a position lower than the lowermost surfaceof the wiring W1 (that is, at a position close to the semiconductorsubstrate 1S). Therefore, the length L1 a is longer than the length L1(that is, “L1 a>L1”). That is, a distance (corresponding to the lengthL1) from the lower surface of the wiring W1 (more specifically, thelowermost surface of the wiring W1) to the upper surface of the plug PL1is smaller than a distance (corresponding to the length L1 a) from thelower surface of the wiring W1 a (more specifically, the lowermostsurface of the wiring W1) to the upper surface of the plug PL1 a.Therefore, it can be said that the reliability of the connection betweenthe plug PL1 a and the wiring W1 a is higher than the reliability of theconnection between the plug PL1 and the wiring W1. However, since thedepth of the wiring W1 a formed inside the insulating film SO is deeperthan the depth of the wiring W1 formed inside the insulating film SO,the distance between the gate electrode G1 and the wiring W1 a isshorter than the distance between the gate electrode G1 and the wiringW1.

Hereinafter, a method of manufacturing the semiconductor deviceaccording to the sixth embodiment will be explained with reference tothe drawings. FIGS. 51 and 52 are cross-sectional views of principalparts of the semiconductor device of the sixth embodiment in amanufacturing step, and illustrate cross sections corresponding to thoseof the above-described FIG. 50 (cross-sectional views of the crosssection A and the cross section C).

Also in the sixth embodiment, the steps illustrated in FIGS. 4 to 10 ofthe above-described first embodiment are performed similarly to those ofthe above-described first embodiment. Note that not only the contacthole CNT1 but also the contact hole CNT1 a are formed in the interlayerinsulating film PIL in the step of the above-described FIG. 6, and thebarrier conductor film PBM and the conductor film TF are formed so as tobe buried inside the contact hole CNT1 and inside the contact hole CNT1a in the step of the above-described FIG. 7. Also, in the step of theabove-described FIG. 8, unnecessary portions of the conductor film TFand the barrier conductor film PBM formed outside the contact holes CNT1and CNT1 a are removed by a CMP method so as to form the plug PL1 andthe plug PL1 a. At this time, the plug PL1 a is formed of the barrierconductor film PBM and the conductor film TF buried and remaining insidethe contact hole CNT1. Further, the upper surface of the insulating filmSO (the interlayer insulating film PIL) is made to recede so that theupper surface of the insulating film SO (the interlayer insulating filmPIL) is lower than the upper surface of the plug PL1 and the uppersurface of the plug PL1 a in the step illustrated in the above-describedFIG. 9, and the interlayer insulating film WIL1 is formed on theinterlayer insulating film PIL including portions on the plugs PL1 andPL1 a in the step illustrated in the above-described FIG. 10.

Also in the sixth embodiment, note that, in the following steps, theupper surface of the insulating film SO is synonymously used with anupper surface of the interlayer insulating film PIL, and an inside ofthe insulating film SO is synonymously used with an inside of theinterlayer insulating film PIL.

FIG. 51 illustrates the cross section A and the cross section C at thetime when the step illustrated in the above-described FIG. 10 (the stepof forming the interlayer insulating film WIL1) of the above-describedfirst embodiment ends. As illustrated in FIG. 51, also in the crosssection C as similar to the cross section A, the upper surface of theinsulating film SO is made to recede (is lowered) from the upper surfaceof the plug PL1 and the upper surface of the plug PL1 a, so that a part(an upper portion) of the plug PL1 and a part (an upper portion) of theplug PL1 a protrude from the upper surface of the insulating film SO.

Also, the insulating film IL1 and the insulating film IL2 are formed asthe interlayer insulating film WIL1 in which the first-layer wiring isformed. However, as similar to the above-described first embodiment, theinsulating film IL2 is formed of a SiOC film which is a low dielectricconstant film in order to reduce the inter-wiring capacitance, and theinsulating film IL1 is formed of a silicon oxide film as an insulatingfilm in order to prevent the abnormal electrical discharge caused whenthe insulating film IL2 is formed of the SiOC film.

In the sixth embodiment, the insulating film IL1 is formed because themanufacturing steps as similar to the manufacturing steps of theabove-described first embodiment are applied. However, if it is notrequired to form the insulating film IL1 as in the above-described thirdand fourth embodiments, the interlayer insulating film WIL1 can beformed of one layer of the insulating film IL2 which is the lowdielectric constant film.

Next, while wiring trenches (the wiring trenches WT1 and WT1 a) areformed as similar to the step illustrated in the above-described FIG. 19of the above-described first embodiment, not only the wiring trench WT1in the cross section A but also the wiring trench WT1 a in the crosssection C are formed in the interlayer insulating film WIL1 asillustrated in FIG. 52. At this time, the wiring trenches WT1 and WT1 aare formed so that the lower surface of the wiring trench WT1 (morespecifically, the lowermost surface of the wiring trench WT1) is at aposition lower than the upper surface of the plug PL1, and so that thelower surface of the wiring trench WT1 a (more specifically, thelowermost surface of the wiring trench WT1 a) is at a position lowerthan the upper surface of the plug PL1. A width of the wiring trench WT1a is larger than a width of the wiring trench WT1.

Note that, for easily understanding, in FIG. 52, the width of the wiringtrench WT1 a is provided with a reference symbol WT1 aW so as to berepresented as a width WT1 aW of the wiring trench WT1 a, the width ofthe wiring trench WT1 is provided with a reference symbol WT1W so as tobe represented as a width WT1W of the wiring trench WT1, and the widthWT1 aW of the wiring trench WT1 a is larger than the width WT1W of thewiring trench WT1 (that is, “WT1 aW>WT1W”). Here, the width (WT1 aW) ofthe wiring trench WT1 a is equal to the width (the above-described widthW1 aW) of the wiring W1 a buried inside the wiring trench WT1 a (thatis, “WT1 aW=W1 aW”), and the width (WT1W) of the wiring trench WT1 isequal to the width (the above-described width W1W) of the wiring W1buried inside the wiring trench WT1 (that is, “WT1W=W1W”). Also, thelowermost surface of the wiring trench WT1 a is at the same position asthat of the lowermost surface W1 aSF of the wiring W1 a in FIG. 53described later, and the lowermost surface of the wiring trench WT1 isat the same position as that of the lowermost surface W1SF of the wiringW1 in FIG. 53 described later.

As similar to the wiring trench WT1 in the cross section A in theabove-described first embodiment, the lowermost surface of the wiringtrench WT1 a in the cross section C is formed inside the insulating filmSO. That is, the wiring trench WT1 a is formed inside the interlayerinsulating film WIL1 and inside the insulating film SO. At this time, anembedding depth of a wiring trench WT1 a inside the insulating film SOis larger than an embedding depth of the wiring trench WT1 inside theinsulating film SO. It is considered that this is because of thefollowing reasons.

That is, the wiring trenches WT1 and WT1 a are formed by dry-etching theinterlayer insulating film WIL1 and the insulating film SO by using aphotoresist pattern (a patterned photoresist film) formed by aphotolithography technique as a mask (an etching mask). In this dryetching step, if an opening area of a pattern to be formed is large,reactive gas used upon the dry etching tends to enter therein, andtherefore, the etching tends to proceed. Also, in the process of the dryetching, because of adhesion of a polymer onto side walls of the patternformed by the dry etching, side-wall etching is suppressed, and anopening area to be reacted is decreased as the dry-etching proceeding,and therefore, it is considered that an etching speed changes to begradual in accordance with the opening area. However, if the openingarea is large, this influence is relatively small, and therefore, it isconsidered that the etching tends to further proceed. That is, becausethe width of the wiring trench WT1 a is larger than the width of thewiring trench WT1, the opening area of the wiring trench WT1 a is largerthan the opening area of the wiring trench WT1, and therefore, the depthof the wiring trench WT1 a is deeper than the depth of the wiring trenchWT1 as illustrated in FIG. 52. That is, a state that the wiring trenchWT1 a is embedded inside the insulating film SO deeper than the wiringtrench WT1 is provided. Therefore, the lowermost surface of the wiringtrench WT1 a is positioned lower than the lowermost surface of thewiring trench WT1, and, when the lowermost surface of the wiring trenchWT1 a and the lowermost surface of the wiring trench WT1 are comparedwith each other, the lowermost surface of the wiring trench WT1 a isformed at a position (a height) closer to the gate electrode G1. When aconductive film is buried in the wiring trench WT1 and the wiring trenchWT1 a in a later step so as to form the first-layer wiring, if adistance between the lower surface of the wiring trench WT1 a and thegate electrode is too short, there is a possibility of the reduction inthe reliability between the first-layer wiring and the gate electrodeG1. Therefore, it is required to form the wiring trench WT1 a so as toensure the reliability between the first-layer wiring and the gateelectrode G1 in consideration of the embedding depth inside theinsulating film SO. The depth of the wiring trench WT1 a is, forexample, 105 to 110 nm. Also, the lowermost surface of the wiring trenchWT1 a is formed at a position lower than the upper surface of the plugPL1 a, and besides, is formed at a position, for example, 20 to 25 nmlower than the upper surface of the insulating film SO.

The step of forming the wiring trenches WT1 and WT1 a is performedsimilarly to the step of forming the wiring trench WT1 in theabove-described first embodiment. As similar to the plug PL1, by theetching for forming the wiring trenches WT1 and WT1 a, at least a partof an upper surface (an upper portion) of the plug PL1 a and a part ofside surfaces thereof are exposed. Note that the plug PL1 is exposedfrom the wiring trench WT1, and note that the plug PL1 a is exposed fromthe wiring trench WT1 a. Therefore, when the conductive film is buriedin the wiring trench WT1 a in a later step, the plug PL1 a and theconductive film buried in the wiring trench WT1 a can be reliablyconnected to each other.

On the other hand, by the step illustrated in the above-described FIG. 8of the above-described first embodiment, the plug PL1 and the plug PL1 aare formed at almost the same height as each other. However, asdescribed above, when the lowermost surface of the wiring trench WT1 aand the lowermost surface of the wiring trench WT1 are compared witheach other, the lowermost surface of the wiring trench WT1 a is formedat a position lower than the lowermost surface of the wiring trench WT1.Therefore, a distance of a portion of the side surfaces of the plug PL1a which is exposed from the wiring trench WT1 a (although a distance inthe direction perpendicular to the semiconductor device 1S) is largerthan a distance of a portion of the side surfaces of the plug PL1 whichis exposed from the wiring trench WT1 (although a distance in thedirection perpendicular to the semiconductor device 1S). That is, adistance L1 b from the lower surface of the wiring trench WT1 (morespecifically, the lowermost surface of the wiring trench WT1) to theupper surface of the plug PL1 is smaller than a distance L1 c from thelower surface of the wiring trench WT1 a (more specifically, thelowermost surface of the wiring trench WT1 a) to the upper surface ofthe plug PL1 a (that is, “L1 b<L1 c”). This distance L1 b indicates theabove-described length L1 obtained after the formation of the wiring W1(that is, “L1 b=L1”), and this distance L1 c corresponds to theabove-described length L1 a obtained after the formation of the wiringW1 a (that is, “L1 c=L1 a”).

In this step, after the dry etching for forming the wiring trenches WT1and WT1 a, there is a possibility that the insulating film IL1 remainson side walls of the plugs PL1 and PL1 a to be exposed from the wiringtrenches WT1 and WT1 a. However, if it remains, it is preferred toremove the insulating film IL1 remaining on the side walls of the plugsPL1 and PL1 a by performing wet etching or others after this dry etchingso as to expose the side surfaces of the plugs PL1 and PL1 a from thewiring trenches WT1 and WT1 a. In this manner, an exact connectionbetween the wirings W1 and W1 a to be formed in a later step and theplugs PL1 and PL1 a can be ensured.

Next, as similar to the steps illustrated in the above-described FIGS.20 and 21A of the above-described first embodiment, the wirings W1 andW1 a are formed as illustrated in the above-described FIG. 50 by formingthe barrier conductor film WBM and the conductor film CUF so as to beburied inside the wiring trenches WT1 and WT1 a, and removingunnecessary portions of the conductor film CUF and the barrier conductorfilm WBM formed outside the wiring trenches WT1 and WT1 a by using a CMPmethod. The wiring W1 is formed of the conductor film CUF and thebarrier conductor film WBM buried and remaining inside the wiring trenchWT1, and the wiring W1 a is formed of the conductor film CUF and thebarrier conductor film WBM buried and remaining in the wiring trench WT1a. Since a part of the plug PL1 a is exposed from the wiring trench WT1a, the wiring W1 a buried in that wiring trench WT1 a is connected tothe plug PL1 a. Also, since a part of the plug PL1 is exposed from thewiring trench WT1, the wiring W1 buried in that wiring trench WT1 isconnected to the plug PL1.

The depth of the wiring W1 a is similar to the depth of the wiringtrench WT1 a, which is, for example, 105 to 110 nm, in which thelowermost surface of the wiring W1 a is positioned lower than the uppersurface of the plug PL1 a, and besides, is positioned, for example, 20to 25 nm lower than the upper surface of the insulating film SO. Thelowermost surface of the wiring trench WT1 a is formed at a position(height) closer to the gate electrode G1 than the lowermost surface ofthe wiring trench WT1, and therefore, the lowermost surface of thewiring W1 a is formed at a position (height) closer to the gateelectrode G1 than the lowermost surface of the wiring W1. However, alsoin the sixth embodiment, by forming the plug PL1 so as to protrude fromthe insulating film SO as similar to the above-described firstembodiment, the connection between the plug PL1 and the wiring W1 can beensured even if the depth of the portion of the wiring W1 which isformed inside the insulating film SO is decreased, and therefore, thedepth of the portion of the wiring W1 a formed in the same step as thatof the wiring W1 and formed inside the insulating film SO is decreased.Therefore, also in the sixth embodiment, surface areas of the wirings W1and W1 a inside the insulating film IL2 which is the low dielectricconstant film are larger than that in the case of the manufacturing stepof the above-described comparative example, and therefore, the increasein the inter-wiring capacitance can be avoided.

Also, as similar to the wiring W1, the depth of the portion of thewiring W1 a which is formed inside the insulating film SO is alsodecreased, and therefore, the shortening of the distance between thewiring W1 and the gate electrode G1 is avoided simultaneously withavoiding the shortening of the distance between the wiring W1 a and thegate electrode G1. Therefore, the reduction in the reliability betweenthe wiring W1 and the gate electrode G1 and the reduction in thereliability between the wiring W1 a and the gate electrode G1 can beavoided. In the sixth embodiment, the case that the insulating film IL2is formed of the low dielectric constant film has been explained.However, regarding the effect of avoiding the reduction in thereliability between the wiring W1 and the gate electrode G1 and thereduction in the reliability between the wiring W1 a and the gateelectrode G1, it is not always required to form the insulating film IL2by the low dielectric constant film. In this case, the insulating filmIL2 can be formed of, for example, a silicon oxide film as an insulatingfilm.

In the sixth embodiment, the above-described effect can be obtained aslong as the upper surfaces of the plug PL1 and the plug PL1 a are formedso as to be even slightly higher than the upper surface of theinsulating film SO as similar to those of the above-described first tofifth embodiments. Here, a more preferable condition used when the plugsPL1 and PL1 a and the wirings W1 and W1 a are formed will be explained.

FIG. 53 is enlarged cross-sectional views of principal parts(partially-enlarged cross-sectional views) of an enlarged periphery of aregion in which the plug PL1 and the wiring W1 are connected to eachother and an enlarged periphery of a region in which the plug PL1 a andthe wiring W1 a are connected to each other in FIG. 50. Hereinafter,with reference to FIG. 53, a more preferable condition for the formationof the plugs PL1 and PL1 a and the wirings W1 and W1 a will beexplained.

The conditions for the length L2 and the length L3 for the plug PL1 andthe wiring W1 are similar to the conditions explained in theabove-described first embodiment, and the similar effect can beachieved. Therefore, explanation thereof is omitted here.

For the plug PL1 a and the wiring W1 a, the length L2 is similar to thelength L2 of the above-described first embodiment, and indicates adistance (a length) from the upper surface of the insulating film SO tothe upper surface of the plug PL1 a. That is, a distance (a length) bywhich the plug PL1 a protrudes from the position of the upper surface ofthe insulating film SO is set as the length L2. That is, the length L2is common between the plug PL1 and the plug PL1 a. In the case of theplug PL1, the distance from the upper surface of the insulating film SOto the upper surface of the plug PL1 corresponds to the length L2. Inthe case of the plug PL1 a, the distance from the upper surface of theinsulating film SO to the upper surface of the plug PL1 a corresponds tothe length L2. Meanwhile, the length L12 is a distance (a length) fromthe lowermost surface of the wiring W1 a to the upper surface of theinsulating film SO. Here, in the sixth embodiment, addition of thelength L2 and the length L3 corresponds to the above-described length L1(that is, “L1=L2+L3”), and addition of the length L2 and the length L12corresponds to the above-described length L1 a (that is, “L1 a=L2+L12”).

Note that, for easily understanding, in FIG. 53, the upper surface ofthe insulating film SO is provided with a reference symbol SOSF so as tobe represented as an upper surface SOSF of the insulating film SO, theupper surface of the plug PL1 is provided with a reference symbol PLSFso as to be represented as an upper surface PLSF of the plug PL1, andthe upper surface of the plug PL1 a is provided with a reference symbolPLSFa so as to be represented as an upper surface PLSFa of the plug PL1a. Further, in FIG. 53, the lowermost surface of the wiring W1 isprovided with a reference symbol W1SF so as to be represented as thelowermost surface W1SF of the wiring W1, and the lowermost surface ofthe wiring W1 a is provided with a reference symbol W1 aSF so as to berepresented as the lowermost surface W1 aSF of the wiring W1 a.

As described above, the lowermost surface of the wiring W1 a is formedat a position lower than the lowermost surface of the wiring W1.However, also in this case, it is desired in the plug PL1 a and thewiring W1 a that a relation of “L2>L12” is established between thelength L2 and the length L12 (that is, it is desired that the length L2is larger than the length L12). By establishing the relation of“L2>L12”, the connection between the plug PL1 a and the wiring W1 a inthe direction perpendicular to the semiconductor substrate 1S can beensured as avoiding the increase in the forming amount of the wiring W1a so as to be embedded inside the insulating film SO (that is, an amountcorresponding to the length L12). Also, by avoiding the increase in theembedding amount of the wiring W1 a inside the insulating film SO (thatis, the amount corresponding to the length L12), the ratio of theportion of the wiring W1 a which is formed inside the insulating filmIL2 which is the low dielectric constant film is increased. In otherwords, by avoiding the increase in the forming amount of the wiring W1 ainside the insulating film SO (that is, the amount corresponding to thelength L12), an area where the wiring W1 a and the insulating film IL2which is the low dielectric constant film are in contact with each othercan be increased. Therefore, for example, the inter-wiring capacitancebetween the wiring W1 a and other wiring which is formed in vicinity ofthe wiring W1 a can be reduced. Also, since the shortening of thedistance between the wirings W1/W1 a and the gate electrode G1 isavoided, the reduction in the reliability between the wirings W1/W1 aand the gate electrode G1 can be avoided. More particularly, byshortening the length L12 as small as possible, the portion of theamount of the wiring W1 a which is formed inside the insulating film SOcan be decreased, and therefore, the inter-wiring capacitance can befurther effectively reduced. In the sixth embodiment, by the formationunder a condition of, for example, a relation of “L12=20 to 25 nm”, theabove-described condition (the relation of “L2>L12”) is satisfied.

Steps after that (after the formation of the wirings W1 and W1 a) aresimilar to those of the above-described first embodiment so as to form asecond-layer wiring. However, illustration and explanation thereof areomitted here.

According to the sixth embodiment, after the polishing for forming theplug PL1 ends, the upper surface (the surface) of the insulating film SOis made to recede so that the upper surfaces of the plugs PL1 and PL1 aare higher than the upper surface of the insulating film SO, so that theconnection between the plug PL1 and the wiring W1 and the connectionbetween the plug PL1 a and the wiring W1 a in the directionperpendicular to the semiconductor substrate 1S can be ensured even ifthe embedding amounts of the wirings W1 and W1 a to be formed laterinside the insulating film SO are less than that in the case of themanufacturing step of the above-described comparative example. Further,by forming the wiring W1 and the wiring W1 a so as not to be embeddedinside the insulating film SO deeper than those in the case of themanufacturing step of the above-described comparative example, thesurface areas of the wiring W1 and the wiring W1 a inside the insulatingfilm IL2 which is the low dielectric constant film is increased, andtherefore, the increase in the inter-wiring capacitance can be avoidedeven if the microfabrication of the wiring structure is achieved.

In the sixth embodiment, the case that the semiconductor deviceaccording to the sixth embodiment is manufactured in accordance with themanufacturing steps of the above-described first embodiment. However,the sixth embodiment can be also applied to not only a case that anotherwiring having a different wiring width (a wiring corresponding to thewiring W1 a) is further formed in the above-described first embodimentbut also a case that another wiring having a different wiring width (awiring corresponding to the wiring W1 a) is further formed in theabove-described second to fourth embodiments.

FIG. 54 is a cross-sectional view of a principal part of a semiconductordevice of the sixth embodiment as a first modification example, and FIG.55 is a cross-sectional view of a principal part of a semiconductordevice of the sixth embodiment as a second modification example. Each ofthe semiconductor devices of FIGS. 54 and 55 corresponds to asemiconductor device which further has another wiring W1 a with a largerwiring width than that of the wiring W1 and with the lowermost surfacepositioned so as to be lower than the lowermost surface of the wiring W1in the semiconductor device of the above-described second embodiment.Both of FIGS. 54 and 55 illustrate not only the cross section A (thecross section taken along the line A-A) but also the cross-sectionalview of the cross section C (the cross-sectional view taken along theline C-C), and a structure of the cross section A is the same as thestructure of the cross section A of the semiconductor device of theabove-described second embodiment (in the above-described FIG. 27 or31).

In the semiconductor device of the first modification exampleillustrated in FIG. 54, in the cross section C, the upper surface of theplug PL1 a is formed at a position higher than the upper surface of theinsulating film SO, and the lowermost surface of the wiring W1 a isformed at a position lower than the upper surface of the plug PL1 a, andbesides, is formed inside the insulating film IL1 as similar to the plugPL1 and the wiring W1 in the cross section A of the above-describedsecond embodiment, so that effects similar to those of theabove-described second embodiment can be obtained.

On the other hand, in the second semiconductor device illustrated inFIG. 55, in the cross section C, the upper surface of the plug PL1 a isformed at a position higher than the upper surface of the insulatingfilm SO, and the lowermost surface of the wiring W1 a is formed at aposition lower than the upper surface of the plug PL1 a, and besides, isformed inside the insulating film SO as similar to the plug PL1 and thewiring W1 in the cross section A of the above-described firstembodiment, so that effects similar to those of the above-describedfirst embodiment can be obtained. Note that the structures of the crosssection A in FIGS. 54 and 55 may be the same as the structure of theabove-described FIG. 27 of the above-described second embodiment or thestructure of the above-described FIG. 31 of the above-described secondembodiment.

FIG. 56 is a cross-sectional view of a principal part of a semiconductordevice of the sixth embodiment as a third modification example, and FIG.57 is a cross-sectional view of a principal part of a semiconductordevice of the sixth embodiment as a fourth modification example. Each ofthe semiconductor devices of FIGS. 56 and 57 corresponds to asemiconductor device which further has another wiring W1 a with a largerwiring width than that of the wiring W1 and with the lowermost surfacepositioned so as to be lower than the lowermost surface of the wiring W1in the semiconductor device of the above-described third embodiment.Both of FIGS. 56 and 57 illustrate not only the cross section A (thecross section taken along the line A-A) but also the cross-sectionalview of the section C (the cross-sectional view taken along the lineC-C), and a structure of the cross section A is the same as thestructure of the cross section A of the semiconductor device of theabove-described third embodiment (in the above-described FIG. 34).

In the semiconductor device of the third modification exampleillustrated in FIG. 56, in the cross section C, the upper surface of theplug PL1 a is formed at a position higher than the upper surface of theinsulating film SO, and the lowermost surface of the wiring W1 a isformed at a position lower than the upper surface of the plug PL1 a, andbesides, is formed inside the insulating film IL2 as similar to the plugPL1 and the wiring W1 in the cross section A of the above-describedthird embodiment, so that effects similar to those of theabove-described third embodiment can be obtained.

On the other hand, in the second semiconductor device illustrated inFIG. 57, in the cross section C, the upper surface of the plug PL1 a isformed at a position higher than the upper surface of the insulatingfilm SO, and the lowermost surface of the wiring W1 b is formed at aposition lower than the upper surface of the plug PL1 a, and besides, isformed inside the insulating film SO as similar to the plug PL1 and thewiring W1 in the cross section A of the above-described fourthembodiment, so that effects similar to those of the above-describedfourth embodiment can be obtained.

FIG. 58 is a cross-sectional view of a principal part of a semiconductordevice of the sixth embodiment as a fifth modification example. Thesemiconductor device of FIG. 58 corresponds to a semiconductor devicewhich further has another wiring W1 a with a larger wiring width thanthat of the wiring W1 and with the lowermost surface positioned so as tobe lower than the lowermost surface of the wiring W1 in thesemiconductor device of the above-described fourth embodiment. FIG. 58illustrates not only the cross section A (the cross section taken alongthe line A-A) but also the cross-sectional view of the section C (thecross-sectional view taken along the line C-C), and a structure of thecross section A is the same as the structure of the cross section A ofthe semiconductor device of the above-described fourth embodiment (inthe above-described FIG. 39).

In the semiconductor device of the fifth modification exampleillustrated in FIG. 58, in the cross section C, the upper surface of theplug PL1 a is formed at a position higher than the upper surface of theinsulating film SO, and the lowermost surface of the wiring W1 a isformed at a position lower than the upper surface of the plug PL1 a, andbesides, is formed inside the insulating film SO as similar to the plugPL1 and the wiring W1 in the cross section A of the above-describedfourth embodiment, so that effects similar to those of theabove-described fourth embodiment can be obtained.

Seventh Embodiment

In the above-described sixth embodiment, the interlayer insulating filmPIL is formed of the insulating film SN and the insulating film SOthereon, and the insulating film SO may be formed of any of the O₃-TEOSfilm, the P-TEOS film, and the stacked film formed of the O₃-TEOS filmand the P-TEOS film. On the other hand, in a seventh embodiment, theinsulating film SO is formed of the stacked film of the O₃-TEOS film andthe P-TEOS film thereon.

In the seventh embodiment, as similar to the above-described sixthembodiment, a semiconductor device and a method of manufacturing thesame according to the seventh embodiment will be explained withreference to not only the cross section A but also the cross-sectionalview of the cross section C.

FIG. 59 is cross-sectional views of principal parts of the semiconductordevice according to the seventh embodiment, and illustrates not only thecross section A (the cross section taken along the line A-A) but alsothe cross-sectional view of the cross section C (the cross-sectionalview taken along the line C-C).

A structure of the semiconductor device of the seventh embodimentillustrated in the cross-sectional views of the cross section A and thecross section C of FIG. 59 is different from that of the semiconductordevice illustrated in the cross-sectional views of the cross section Aand the cross section C of the above-described FIG. 50 of theabove-described sixth embodiment in that the insulating film SO isformed of the stacked film formed of the O₃-TEOS film OTS and the P-TEOSfilm PTS thereon. However, other structures of the semiconductor deviceof the seventh embodiment are similar to the structure of thesemiconductor device of the above-described sixth embodiment.

However, as described in the above-described fifth embodiment, theinsulation property of the O₃-TEOS film tends not to be excellent.Therefore, as illustrated in FIG. 59, it is required that the wiring W1a and the O₃-TEOS film OTS are not to be in contact with each other evenif the lowermost surface of the wiring W1 a is formed at a position (aheight) closer to the O₃-TEOS film OTS formed on the gate electrode G1of the re-channel-type MISFET Q₁ in comparing the lowermost surface ofthe wiring W1 a with the lowermost surface of the wiring W1. By such amanner, the reliability between the wirings W1/W1 a and the O₃-TEOS filmOTS can be improved.

As the step of manufacturing the semiconductor device according to theseventh embodiment, upon the formation of the insulating film SO in thestep of manufacturing the semiconductor device according to theabove-described sixth embodiment, the O₃-TEOS film OTS is formed on theinsulating film SN first, and this O₃-TEOS film OTS is buried betweenthe semiconductor elements, and then, the P-TEOS film PTS is formed onthe O₃-TEOS film OTS. By this manner, the insulating film SO is formedof the stacked film formed of the O₃-TEOS film OTS and the P-TEOS filmPTS on the O₃-TEOS film OTS. Other steps are similar to the steps ofmanufacturing the semiconductor device of the above-described sixthembodiment, and therefore, explanation thereof is omitted here.

To the seventh embodiment, the manufacturing steps similar to those ofthe above-described sixth embodiment are applied, and therefore, theinterlayer insulating film WIL1 of the first-layer wiring is formed ofthe insulating film IL1 and the insulating film IL2. However, if it isnot required to form the insulating film IL1 as in the above-describedthird and fourth embodiments, the insulating film WIL1 can be formed ofone layer of the insulating film IL2 which is the low dielectricconstant film.

Also in the seventh embodiment, in a step corresponding to theabove-described FIG. 48 of the above-described sixth embodiment, theupper surface of the P-TEOS film PTS is made to recede so that the uppersurfaces of the plugs PL1 and PL1 a are higher than the upper surface ofthe P-TEOS film PTS. Therefore, even if the wirings W1 and W1 a areformed so that the connection length L1 between the plug PL1 and thewiring W1 in the direction perpendicular to the semiconductor substrate1S is ensured and so that the connection length L1 a between the plugPL1 a and the wiring W1 a in the direction perpendicular to thesemiconductor substrate 1S is ensured, the embedding amounts of thewiring W1 and the wiring W1 a inside the insulating film SO can bedecreased further than that in the case of the manufacturing step of theabove-described comparative example. Therefore, the surface areas of thewiring W1 and the wiring W1 a inside the IL2 which is the low dielectricconstant film are increased, and therefore, the inter-wiringcapacitances for the wiring W1 and the wiring W1 a can be reduced.Further, the wirings W1 and W1 a can be formed so that the distancebetween the wirings W1/W1 a and the gate electrode G1 or the distancebetween the wirings W1/W1 a and the O₃-TEOS film OTS is not shortened ascompared with the manufacturing step of the above-described comparativeexample, and therefore, the reduction in the reliability of the wiringsW1/W1 a for the gate electrode G1 and the O₃-TEOS film OTS can beavoided.

In the seventh embodiment, the case that the insulating film IL2 isformed of the low dielectric constant film has been explained. However,for achieving the effect of avoiding the reduction in the reliabilitybetween the wirings W1/W1 a and the gate electrode G1 or avoiding thereduction in the reliability of the wirings W1/W1 a for the gateelectrode G1 and the O₃-TEOS film OTS, it is not always required thatthe insulating film IL2 is formed of the low dielectric constant film.In this case, the insulating film IL2 can be formed of, for example, asilicon oxide film as the insulating film.

By setting a preferable condition used when the wiring W1 is formed tothe plug PL1 so as to be similar to the condition of the above-describedsixth embodiment, effects similar to those of the above-described sixthembodiment can be obtained, and besides, the reduction in thereliability of the wirings W1/W1 a with respect to the O₃-TEOS film OTScan be avoided.

In the seventh embodiment, the case that the insulating film SO of thesemiconductor device corresponding to the above-described FIG. 50 of theabove-described sixth embodiment is formed of the stacked film formed ofthe O₃-TEOS film OTS and the P-TEOS film PTS thereon has beenexemplified. However, the insulating film SO of each of thesemiconductor devices corresponding to the above-described FIGS. 54 to58 of the above-described sixth embodiment can be also formed of astacked film formed of the O₃-TEOS film OTS and the P-TEOS film PTSthereon. Also in this case, the effects explained in the above-describedsixth embodiment can be obtained, and besides, the reduction in thereliability of the wirings W1/W1 a with respect to the O₃-TEOS film OTScan be avoided.

In the foregoing, the invention made by the present inventor has beenconcretely described based on the embodiments. However, it is needlessto say that the present invention is not limited to the foregoingembodiments and various modifications and alterations can be made withinthe scope of the present invention.

INDUSTRIAL APPLICABILITY

The present invention is effectively applied to a semiconductor deviceand a method of manufacturing the same.

SYMBOL EXPLANATION

1S, 101S semiconductor substrate

CF101, CF102 conductive film

CNT1, CNT2, CNT101 contact hole

CUF, CUF2 conductor film

EX1, EX101 shallow impurity diffusion region

G1, G101 gate electrode

GI1, GI101 gate insulating film

IL1, IL2, IL3, IL4 insulating film

L1, L1 a, L2, L3, L4, L5, L6 length

L7, L8, L9, L10, L11, L12, L101 length

L21 thickness

LM lower-layer material

ML middle layer

NR1, NR101 deep impurity diffusion region

NS1 n-type semiconductor region

NSF1, NSF101 metal silicide layer

OTS101 O₃-TEOS film

PBM barrier conductor film

PIL, PIL101 interlayer insulating film

PL1, PL1 a, PL101, PL2 plug

PLSF, PLSFa upper surface

PS1 p-type semiconductor region

PS2 p-type semiconductor region

PTS101 plasma TEOS film

PWL1, PWL101 p-type well

Q₁ n-channel-type MISFET

Q₂ p-channel-type MISFET

SN insulating film

SN101 silicon nitride film

SO insulating film

SOSF upper surface

STI, STI101 element isolation region

SW1, SW101 sidewall

TF conductor film

TH1, TH2, TH3 through hole

UR upper-layer resist film

W1, W1 a, W101 wiring

W1W, W1 aW width

W1SF, W1 aSF lowermost surface

WBM, WBM2 barrier conductor film

WIL1, WIL2, WIL101 interlayer insulating film

WT1, WT1 a, WT2, WT101 wiring trench

What is claimed is:
 1. A semiconductor device comprising: a firstinterlayer insulating film formed on a semiconductor substrate; a firstplug formed inside the first interlayer insulating film; a secondinterlayer insulating film formed on the first interlayer insulatingfilm and having a dielectric constant lower than a dielectric constantof silicon oxide; and a first buried wiring formed inside the secondinterlayer insulating film and connected to the first plug, an uppersurface of the first plug being formed at a position higher than anupper surface of the first interlayer insulating film, and a lowersurface of the first buried wiring being formed at a position lower thanthe upper surface of the first plug.